JPH01232441A - Parity counting circuit - Google Patents

Abstract

PURPOSE:To securely count the parity of even fast data by resetting the output of a JK flip-flop at a frame period and using the output of the JK flip-flop right before resetting as a parity counting output. CONSTITUTION:Two sequences of data D1 and D2 which are inputted to an exclusive OR circuit 11 are obtained by dividing one sequence of original data into two sequences by series/parallel conversion, so the data speed is halved. Those sequences of data are inputted to an exclusive OR circuit 11 and ORed. The OR result data is in one sequence and inputted to the JK flip-flop 12, and its speed is 1/2. Consequently, the margin of reset pulses inputted to the JK flip-flop 12 is increased double and respective frames can be reset with the margin, so that the parity of even fast data can securely be counted.

Description

[Detailed Description of the Invention] [Summary 1] Regarding a parity counting circuit that counts parity days of high-speed data, the purpose is to perform parity counting reliably even in the case of high-speed data, and to perform an exclusive OR of data of two systems. and a JK flip-flop that receives the output of the exclusive OR circuit, and resets the output of the JK flip 70 at a frame period, and resets the output of the JK flip-flop immediately before reset.
The output of the flip-flop is configured to be a parity count output.

[Industrial Application Field] The present invention relates to a parity counting circuit that counts the parity of high-speed data.

In the field of data transmission, when transmitting data at high speed, parity is added to each frame and a parity check is performed on the receiving side to confirm whether the data has been transmitted correctly. As is well known, parity checks include even parity and odd parity, and the sending and receiving sides agree in advance which one to use.
Third, by checking the parity of each transmitted frame on the receiving side, it is determined whether the data transmission was performed correctly. Such a parity count is determined by counting the number of "1"s in the data for each frame on the receiving side, and determining whether there is an even number or an odd number. This is called parity counting.

[Prior Art] FIG. 5 is a conceptual diagram of a conventional parity 11 circuit. In the figure, 1 is a first flip-flop that receives high-speed data at clock input CK and reset pulse at ret R, and its Φ output and D input are connected to 1/
It constitutes a 2 frequency divider. 2 receives the Q output of the first 7-lip flop 1 at its D input, and receives a frame pulse at its clock input CK for synchronizing the frame and the counting results.
It is a flip 70 tube.

FIG. 6 is a timing chart showing the operation of FIG. In the figure, (a) is a symbol indicating the frame interval, (b) is data, and (c) and (d) are reset pulses. This reset pulse is a pulse for resetting the counting result for each frame because a parity check is performed for each frame. The width of this reset pulse is normally set to less than half the width of the frame pitch i-F. In the data shown in (b), l) n is the final data of the previous frame,
F is the frame number i which indicates the beginning of the frame, and D1 and subsequent parts are the data portions.

In order to correctly calculate the parity numerical value for each frame in such a configuration, the reset pulse must always come before the frame bit F, as shown in <C). In other words, if a reset pulse as shown in (c) is always applied, the second flip-flop 2 will output an accurate variation check result. J3, from flip-flop 2, for example, in the case of even parity, l l IT
, in the case of odd parity, the counting result is output in the form of 0''.

[Problems to be Solved by the Invention] However, in reality, the arrival of the reset pulse is delayed due to delays due to gate delays in the circuit or rounding of the waveform due to stray capacitance existing in the wiring pattern, and as shown in FIG.
As shown in d), the edge of the reset pulse may exceed frame bit F. In this case, the data D1 portion will be ignored, making it impossible to perform a correct parity check. Such a phenomenon is particularly likely to occur in the case of high-speed data transmission, for example, several hundred MHz. Further, it is also difficult to match the phase using the frame pulse using the second 7-lip 70-tube 2, considering the amount of circuit variation.

In order to solve this problem, two circuits as shown in FIG. 5 may be provided and parity checks may be performed alternately. In this way, since the reset pulse only needs to be generated once every two frames, the margin becomes large and the parity 51 number can be calculated accurately.

However, in this case, the number of circuit elements increases, which becomes an obstacle when designing a high-density IC.

The present invention has been made in view of these points, and
Parity itr allows you to perform parity counting reliably even in the case of high-speed data! The purpose is to provide an i-circuit.

[:! Means for Solving Problem R] FIG. 1 is a block diagram of the principle of the present invention. In the figure, 11 is an exclusive OR circuit that takes the exclusive OR of two series of data D1 and 02, and 12 is an exclusive OR circuit 11.
This is a JK flip-flop that receives the output (Q) of . Here, two series of data entering the exclusive OR circuit 11 [)
1, [)2 serially converts the initial series of high-speed data.
Assume that the data has been converted into two series of data through parallel conversion. A reset pulse is input to the reset input R of the JK flip 70 knob 12.

[Operation] Two series of data D1 and D2 entering the exclusive OR circuit 11
is obtained by serial/parallel converting the original one series of data and dividing it into two series, so the data rate is 1/2. The exclusive OR circuit 11 contains these two series of data DI and D2, and these two series of data enter the exclusive OR circuit 71 and are logically summed. The resulting data enters the JK flip-flop 12 as one series, but its speed is also 1/2.

Therefore, the margin of the reset pulse entering the JK flip-flop 12 is increased by twice, and each frame can be set with sufficient margin.

FIG. 2 is a timing chart showing the effect of the present invention.
The reset pulse shown in (b) can perform a reset at the start of each frame with a sufficient margin for the data string shown in (a) (the logical ORed data). Therefore, if the output of the JK flip-flop 12 immediately before this relet is taken out, this will represent the parity count output of the frame.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a configuration block diagram showing one embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals.

In the figure, 21 is an exclusive OR circuit consisting of gates G1 to G3, and 22 and 23 are D-type flip-flops. Reference numeral 12 denotes the above-mentioned JK flip-flop, which is composed of gates G4 to G6 and a D-type flip-flop 24.

25 is a D type flip-flop which receives the output of the JK flip-flop 12 at its C input, and the Q output of the flip-flop 25 serves as a parity counting output.

The exclusive OR circuit 21 has two series of data D1 and D2.
and an inhibit signal I that prohibits input of these data.
N+-11 and lNl-12 are included, respectively. When these inhibition signals INH1 and INH2 are at the "1" level, the data D1. Input of D2 is prohibited. The output of the exclusive OR circuit 21 is input to the C input of the flip-flop 22, and the C input of the flip-flop 22 receives the high-off pulse CLK. Then, the Q output of the flip 70 tube 22 is input to the J input of the JK flip-flop 12.
◇It is included in both the output and input. Also flip 7
The C input of the 0-tube 23 receives a reset pulse, and the C input receives a clock pulse CLK.

The Q output of the flip-flop 70 tube 23 enters the gates G4 and G5 of the JK flip-flop 12, and the Q output enters the C input of the flip-flop 25.

Further, the clock pulse CLK is applied to the flip-flop 24.
It is also included in the C input. The operation of the circuit configured as described above will be explained below with reference to the timing chart shown in FIG.

Data D1. In addition to the frame bit F, D2 includes service bits C and SC as shown in FIG. During parity counting, it is necessary to prohibit these service bits, so the service bit C and frame bit F of Dl are prohibited at IN 11 shown in (d), and the service bit C and frame bit F shown in (e) are disabled.
Service bits C and SC of D2 are prohibited in H2. Two series of data D with these bits prohibited
1°D2 enters the exclusive OR circuit 21 and is converted into one series of data strings. When the data is converted into one series of data, the speed has dropped to 1/2. This JJ+
The output of the alistic OR circuit 21 is C of the flip-flop 22.
The reset pulse that enters the input and shown in (to) is the flip 7
Enter C input of 0 knob 23. The signals input to these C inputs are synchronized by the clock pulse CLK shown in (a), and are outputted from the respective Q outputs in the form (phase aligned).

First, when the reset pulse shown in <<>> is input, the JK flip-flop 12 and the subsequent flip-flop 25 are set to I for the first time.
It is converted into ll value. The model, the JK flip-flop 1
2 counts the output of the exclusive OR circuit 21. The count does not count up when Dl and 1]2 are the same, and counts up only when they are different. These count values are output via the flip-flop 25 as a parity count output. In this series of operations, according to the present invention, parity counting is divided into two series and processed in parallel, so the circuit can be reliably reset before the start of counting of each frame, thus ensuring reliable parity. Can perform counting.

Further, since the circuit of the present invention has a small number of gates, it is suitable for integration, and the amount of delay caused by connecting gates in multiple stages can be reduced, which is advantageous.

[Advantageous Effects of the Invention 1] As explained above, according to the present invention,
Since high-speed transmission data is serial-parallel converted into two series of data and the transmission speed is reduced to 1/2, it is possible to easily increase the operating margin due to variations in gate delay amount. Resetting can be performed reliably for each frame data string, and parity counting can be performed reliably even in the case of high-speed data.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a timing chart showing the operation of the present invention, Fig. 3 is a configuration block diagram showing an embodiment of the present invention, and Fig. 4 is the operation of the circuit shown in Fig. 3. FIG. 5 is a conceptual diagram of a conventional parity counting circuit, and FIG. 6 is a timing chart showing the operation of FIG. In FIG. 1, 11 is an exclusive OR circuit, and 12 is a JK flip-flop. Patent applicant: Fujitsu Limited
company+71111

Claims (1)

[Claims] An exclusive OR circuit (11) that takes the exclusive OR of two series of data D1 and D2, and a JK flip-flop (12) that receives the output of the exclusive OR circuit (11). and said J in a frame period.
A parity counting circuit configured to reset the output of the K flip-flop (12) and use the output of the JK flip-flop (12) immediately before the reset as a parity counting output.