JPS58188952A - Parallel serial data transmitting circuit - Google Patents

Abstract

PURPOSE:To secure parallel serial data transmission, by dividing the frequency of a system clock and generating a transmission reception system shift clock, and setting the speed of the system clock optionally while varying a frequency division ratio. CONSTITUTION:A frequency divider C divides the frequency of system clock (a) and supplies the frequency-divided signal (d) to a clock control circuit E. A shift register A converts parallel data into serial data (h) in response to a system clock (f) and outputs the serial data. In this case, a shift counter B counts the shift clock, and when its counted value reaches a specific value, the clock control circuit E is controlled to stop the transfer of the shift clock from the circuit C to the register A. Further, a strobe signal (g) and a stop signal (e) are generated according to the counted value of the counter B.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel/serial data transmission circuit for transmitting digital signals via an eye inverter.

FIG. 1 is a conceptual diagram of digital signal transmission. In the figure, when transmitting a digital signal from a transmitting system 1 to a receiving system 3, an isolator (for example, a photocoupler) 2 is used. This is to separate the grounds for the transmitting system and the receiving system to eliminate the influence of noise. In order to reduce the number of signal lines and isolators and to eliminate the influence of noise, parallel data is converted into serial data and transmitted. That is, a parallel to serial conversion circuit (shift register) 4 is provided in the transmission system 1 and a serial to parallel conversion circuit (shift register) 5 is provided in the reception system 3, and serial data 7 is transmitted. A shift clock 8 is transmitted in order to synchronize with the system 3. Also, a memory circuit 6 is used in the reception system 3 to memorize the output of the serial/parallel conversion circuit 5. A strobe signal 9 is transmitted to enable the memory circuit 6 to receive data.
Data 7, shift clock 8 and strobe signal 9 are transmitted via isolator 2.

However, the conventional circuit has the following drawbacks.

As a clock signal that generates or controls data signals, system clocks, and strip signals, the clock used for the microprocessor in the transmission system is used as is. As a result, the equivalent speed of the isolator cannot follow the clock speed (transmission speed), and reliable data transmission cannot be performed.Recently, microprocessors have become faster, and this problem has been solved by the author of 4IKIl. It has become.

Therefore, the main object of the present invention is to provide a parallel/serial data transmission circuit that can easily obtain a transmission speed (transmission lock) that matches the response speed of the isolator used and can perform data transmission reliably. be.

Another object of the present invention is to use a synchronous reset path to stop the shift operation after the data has been reliably transmitted from the transmitting system to the receiving system, and to prevent erroneous data from being transmitted. Furthermore, after the shift operation is stopped, a strobe signal matching the response speed of the isolator is sent to realize reliable data transfer within the receiving system. The present invention will be explained below using the drawings.

FIG. 2 shows a parallel/serial system according to an embodiment of the present invention.
FIG. 2 is a block diagram of a data transmission circuit. This transmission circuit constitutes a transmission system. The transmission circuit includes a shift register A (8 bits in this embodiment) that receives parallel data and sends out serial data h, and a shift counter that counts the number of shifts in shift register A and generates a strobe signal g and a stop signal. B, divide the system clock,
A system clock divider C supplies the division signal d as the transmission system shift clock f to the shift register A and generates the reception system shift clock e, and receives the output signal d and control signal of the frequency divider 4C, and receives the transmission system shift clock f and generates the reception system shift clock e. A clock control circuit E that controls sending and stopping of signals f and e receives a start signal and a stop signal from shift counter B, sends a shift counter BK clear signal (and sends a clock control circuit Elc control signal) Serial data h, strobe signal g, and reception system shift clock e are sent from the transmission circuit, and these signals are sent to the reception system via an isolator. .7 In the conventional circuit consisting of a register and shift counter B,
The elements C, D, and E are added.

Next, the operation of the circuit shown in FIG. 2 will be explained. FIG. 3 is a waveform diagram of each part of the circuit of FIG. 2. a is a high-speed system clock used to control the microprocessor in the transmission system. Parallel data is loaded into the shift register AVC in response to the start signal f, and thereafter the shift register AVC is loaded with parallel data in response to the start signal f.
In response to this, a signal is sent serially one pit at a time. The divider C divides the system clock a into l/
4) Generate a branch signal d that matches the corresponding speed of the isolator. In response to the start signal S, the branch signal d passes through the control circuit E, and the transmission/reception system shift clock f.

e is generated, serial data is transmitted bit by bit, and the receiving system receives the serial data in response to the shift clock e. Note that e lags f by half a cycle, and reliable data reception is performed in the receiving system. The number of shift clocks sent out is counted by a shift counter B, and when eight shift clocks corresponding to the number of bits of the shift register are generated, a strobe signal g and a stop signal are generated. Therefore, the start-stop circuit is reset, transmission of the shift clock is stopped, and shift counter B is reset.

As is clear from the explanation below, the transmission/reception system shift clock is generated by dividing the system clock.
The speed of the shift clock can be set arbitrarily by changing the division ratio. Therefore, the speed of the shift clock can be determined in accordance with the response speed of the isolator, and reliable data transmission can be achieved.

FIG. 4 is a block diagram of a parallel serial data transmission circuit according to another embodiment of the present invention.

The same parts as in FIG. 2 are given the same reference numerals. The circuit of FIG. 4 improves on the drawbacks of the circuit of FIG. 2. Referring again to FIGS. 2 and 3, the strobe signal g is generated after the count of eight shift pulses by the shift counter BK and is immediately thereafter reset by the start/stop circuit. Therefore, the width of the strobe signal is narrow, and the strobe signal is not transmitted reliably due to the characteristics of the isolator.
Data transfer is not performed reliably in the receiving system.

The circuit shown in FIG. 4 is intended to overcome this problem.

The circuit of FIG. 4 receives the output signals of a system clock divider C and a shift counter B in addition to the shift register A, shift counter B1 and system clock divider C described above, and receives a strobe signal m and a shift counter reset signal n. Synchronous shift counter reset circuit E that generates
, a reception system shift clock generation circuit F that receives the shift clock signal and the output signal of the shift counter B and generates the reception system shift clock l, receives the load signal S and the output signal n of the synchronous shift counter reset circuit E. , transmission/reception, and a clock signal control circuit G for controlling sending and stopping of shift clocks in the transmission system.

Next, the operation of the circuit shown in FIG. 4 will be explained. FIG. 5 is a waveform diagram of each part of the circuit of FIG. 4. The operation of shift register A is the same as in FIG. The divider C generates a frequency-divided signal J, which is the basis of the shift clock, and a signal i faster than J. When shift counter B counts eight shift clocks, signal R becomes 1". Then, in synchronization with the next rising edge of signal i, shift counter reset circuit E generates strobe signal m and shift counter reset signal n. As a result, the clock signal control circuit G is reset or disabled;
Sending of the shift clock is stopped (by signal P).

Thereafter, strobe signal m returns to C in response to frequency-divided signal i. In this way, the final data in shift register A (
After bit 7) has been transmitted, the transmission of the shift clock will be stopped after a certain period of delay (half a period relative to the shift clock), and then a strobe signal m with a pulse width equal to the speed of the shift clock will be generated. After signal transmission, a sufficiently wide sweep signal is generated to match the response speed of the isolator.

As is clear from the above description, according to the present invention, data transmission can be performed reliably in accordance with the characteristics of the isolator, and strobe signals can be reliably transmitted to the receiving system.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of digital signal transmission, Fig. 2 is a block diagram of a parallel/serial data transmission circuit according to an embodiment of the present invention, Fig. 3 is a waveform diagram of each part of the circuit in Fig. 2, and Fig. 4 is a block diagram of a parallel/serial data transmission circuit according to an embodiment of the present invention.
The figure is a block diagram of a parallel/serial data transmission circuit according to another embodiment of the present invention, and FIG. 5 is a waveform diagram of each part of the circuit of FIG. 4. Transmission system, 2 near isolator, 3: Receiving system, 4: Parallel/serial conversion circuit, 5 Nijirial parallel conversion circuit, 6: Memory circuit, A: Shift register, B: Shift counter, C: Frequency divider, D Ni start-stop circuit,
E: clock control circuit, F: reception system shift clock generation circuit, G: clock signal control circuit. Ken - Kazuichi Tsuyoshi

Claims (1)

[Claims] a frequency divider that divides the system clock and generates a shift clock; a conversion circuit that converts parallel data into serial data and sends it out in response to the shift clock; and a conversion circuit that counts the shift clock and makes sure that the counted value becomes a scheduled value. a control circuit for stopping the transfer of the shift clock from the branching unit to the conversion circuit and generating a strobe signal.