JPS61152140A - Data synchronizing circuit - Google Patents

Abstract

PURPOSE:To generate a clock synchronous with a signal whose noise has been removed and to reduce an erroneous discrimination of 'L' or 'H' of an input signal by detecting the edge of an input digital signal and counting the length of an interval between edges. CONSTITUTION:The 1st edge detecting circuit 12 detects a signal 14 for discrimi nating whether the edge signal 13 of the digital signal 11 is 'H' or 'L', and the signal 13 sets the 1st counting circuit 16. The circuit 16 counts a signal 15 during setting, and applies a signal 17 to AND gates 20 and 22 after resetting. The signal 14 and its inverted one are applied to the gates 22 and 20, respective ly, which generate reset signals 21 and set signal 23, respectively, and apply them to a flip-flop circuit 24. The 2nd edge detecting circuit 26 detects the rise of the output signal 25 of the circuit 24, and an edge signal 27 sets the 2nd counting circuit 29. An AND signal 32 between counting signals 30 and 27 during setting the circuit 29 sets a state/stop system data synchronizing circuit 34, and a signal 35 is counted until said circuit 34 is reset, thereby outputting the counted signal 35.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a clock recovery method for synchronizing digital signals.

[Background of the invention]

A conventional data synchronization circuit, as described in Japanese Unexamined Patent Publication No. 58-56212, synchronizes at edges when the edge interval of a digital signal is a predetermined interval.

There is no problem when detecting a falling edge 4 of a digital signal 3 obtained by slicing an ideal signal 1 at a slice level 2 as shown in FIG.

However, in the digital signal 7 obtained by slicing the noise-containing signal 5 at the slice level 6 as shown in FIG. 3, a short pulse appears near where the signal 5 crosses the slice level 6. At this time, signals 9, 10, etc. appear as a result of noise on signal 8, which detects the falling edge of the digital signal, resulting in a problem that synchronization is disturbed.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art by eliminating short pulses that are noise in the input signal, thereby achieving synchronization only with edges at intervals allowed by the format, and achieving data synchronization. The goal is to eliminate disturbances and reproduce a stable clock.

[Summary of the invention]

In order to achieve the above object, the present invention has the following features.

detects the edges of the input digital signal and removes short pulses by counting the length of the interval between edges;
This is to synchronize data with the removed signal.

In other words, when considering the noise level of a signal before it is converted into a digital signal, its C/N is usually 30 dB to 40 dB, so as shown in Figure 3, the noise level in the vicinity where the signal crosses the slice level is Noise appears in digital signals as short pulses.

In the present invention, in order to eliminate the influence of this short pulse, edges of the input digital signal are detected.

By counting the length of the interval between edges, short pulses are removed and data synchronization is achieved with the removed signal.

[Embodiments of the invention]

The present invention will be explained in detail using a specific example. @1
The figure shows the configuration of a data synchronization circuit including the present invention.

The first edge detection circuit 12 receives the digital signal 11 and outputs an edge signal 13 and a discrimination signal 14 which becomes H when the edge signal 13 is a rising edge and becomes L when it is a falling edge. The counting circuit 16 of W, 1 is set by the sum of the edge signals 13, counts the signal 15 except during this reset period, and outputs the signal 17 after a certain period of time has elapsed after being reset. The AND gate 22 performs the logical product of the 1 discrimination signal 14 and the signal 17.
The AND gate 22 generates the reset signal 21 using the set signal 23 and the signal 17 and the signal 19 obtained by inverting the 1 discrimination signal 14 by the inverter 18 . The tree flop 24 is set to H by the set signal 21 and set to L by the reset signal 23, and outputs a signal 25.

The second edge detection circuit 26 detects the rise of the output signal 25 of the flip-flop 24 and outputs an edge signal 27. The second counting circuit 29 is reset by the edge signal 27, counts the signal 28 except for this reset period, and outputs a predetermined count value signal 30 after being reset. AN
The D gate 31 outputs an AND signal 32 of the edge signal 27 and the count value signal 30. Start-stop data synchronization circuit 34
After being reset by the signal 32, it counts the signal 33 until the primary busy is reset, and outputs a unique count value signal 35.

Next, a more detailed explanation will be given with reference to the time chart shown in FIG.

In this example, the time 392 of the input digital signal 11 and the time 40
L level pulse in the interval and 1 time 43, ll
The H level pulses in the 1m44 interval Ilf:S time 492 and the H level pulses in the time 50 interval are the pulses that should be removed, and the signal 11 is originally a repeat of 2T, where the length of 1 bit is T. Suppose it is a signal. Furthermore, in this example, the signal 15. Signal 28. signal 3
3 is a signal whose period is 1/8 of the length T of the signal 1101 bits.

A signal obtained by delaying the signal 11 by 1, for example, time 36 from the edge signal 13 detected at time 37 is defined as the discrimination signal 14. Furthermore, the count value of f$, 1 of the counting circuit 16 is selected so that the signal 17 is output when one hour 36 has elapsed after the first counting circuit 16 was reset by the edge signal 13. By the length of this time 36.

The length of the pulse to be removed can be determined. In this example, 1
Time 36 is assumed to be V8 with a signal length T of 1101 bits.

At time 38, the determination signal 14 is H and the signal 17 is being output, so the set signal 23 is output and the output 25 of the flip-flop circuit 24 is set to H. Next time 3
The edge signal 13 detected at 9 causes the first counting circuit 1 to
6 will be reset.

Before the length of time 36 has elapsed, the edge signal L3 is further detected at time 40, so that the signal 17 is output at time 41, when the length of time 36 has elapsed from one time 40. At this time, the 1 discrimination signal 14 is from time 40 to time 36.
Since the signal 11 is delayed by the length of ``ff'' level, the set signal 23 is output.

The output 25 of flip-flop 24 at time 41 remains set to H. Therefore time 39° time 4
An L level at 0 does not appear on signal 25.

Similarly, at time 42, the 7 flip-flop 24 is reset by the signal 21, and as a result of the edge signal detected at 1 time 44, the edge signal detected at 1 time 43 is reset at time 45, but the edge signal detected at 1 time 43 is output from the output 25 of the flip-flop 24. It is not reflected in

Therefore, the short width pulse of the input signal 11 cannot be outputted to the output 25 of the 7-lip flop 24.

Next, the second edge detection circuit 26 detects the rising edge signal 27 of the signal 25. The counting circuit 29 of fa2 is 1
It is reset by the rising edge signal 27 at time 37, and in this example, the count signal 30 is output at time 469, time 471, and time 48. At time 47.

Since the edge signal 27 is output, the AND gate 22
An AND signal 32 is output. With AND signal 32, 1J
This is because the counting circuit 34 of IE3 is reset.

In this example, the count value signal 35 of the asynchronous data synchronization circuit 34 becomes short at time 47, and after 1 time 47, the signal 35 in this example becomes shorter.
A signal obtained by dividing 3 by 8 is output as a count value signal 35,
This serves as a synchronization clock for signal 11.

In this example, signal 15. Signal 28. Although the length of the signal 33 is set to T01/8, which is the length of one bit of the input signal 11, the length can be arbitrarily selected. In that case, it is sufficient to change the division ratio of the second counting circuit and the start-stop data synchronization circuit.

Further, in this example, the length of 1 hour 36 is set to 2A, which is the length T of 1101 bits of the input signal, but this length can also be arbitrarily selected.

Further, the edge signal 27 detected by the edge detection circuit 26 of 8I2 may be one obtained by detecting a falling edge.

In FIG. 5, the first edge detection circuit 12. and first counting circuit 16. A more detailed embodiment of the flip-flop circuit 240 will be shown.

The input signal 11 is input to the first stage D-FF 51, and the same output 53
is input to the second stage D-FF 52, and the same output 14 is obtained.

Both outputs 53 and 14 are input to an E-OR circuit 540 to obtain an edge signal 13. Here, the width of the edge output 13 is equal to 550 cycles of the clock pulses of the D-FFs 51 and 52.

The edge signal 13 resets the first counting circuit 16. The first counting circuit is composed of a D-FF 57 with reset, and the ζ output 56 of the D-FF 57 is
Since it is an input, the signal 17 is not connected to the D-FF except for the reset period, that is, the period when the edge signal 13 is output.
57 clock pulse signal 15 divided by two.

The flip-flop circuit 24 is an AND gate circuit 21
, D-F to remove the hazard appearing in the output of 23.
It consists of F58 and 59 and an R-8FF to which the outputs of NAND gate circuits 63 and 64 are fed back.

The clock signal SS of the edge detection circuit 12, the clock signal 15 of the *t counting circuit 16. The signal 25 is obtained by inputting the same signal as the clock signal 62 of the flip-flop circuit 24 and the clock signal 62 of the flip-flop circuit 24.

The time chart diagram of FIG. 5 is shown in the taG diagram.

FIG. 7 shows a second edge detection circuit 26. Second counting circuit 2
9. A more detailed embodiment of the start-stop data synchronization circuit 340 will now be described.

In the second edge detection circuit 26, the signal 25 is
61C is input, and the same output 67 is inputted to the next stage D-FF 69 to obtain the output cuff 0. D-F F 66 and 65 operate simultaneously using a clock signal 65, and input the ζ output 68 of D-FF 66 and the Q output cuff 0 of D-FF 69 to an AND gate circuit 71 to obtain a rising edge signal 27.

The second counting circuit 29 has a D-
FF72 and J-KFF74. 75. It is composed of an 8-frequency divider counter clocked by a clock signal 28 formed by a 76° AND gate circuit 77, and an AND gate 81 that decodes a predetermined count signal 30. Input edge signal 27 to D-FF72, f83 output cuff 3
So J-KFF74. Reset 75° and 76. The count signal 30 is output every eight clock signals 28. Further, the count value signal 30 is generated once the edge signal 27 is output.

It is only necessary to select the time so that it coincides with the time when the next busy edge signal 27 should be output.

AND game 1, edge signal 27 and count value signal 30
The signal 32 is output only when the two inputs match.

Next, the start-stop data synchronization circuit 34 will be explained.

D- whose input is the output signal 32 of the AND gate circuit 31
FF82 is for timing adjustment. J
-KFF84. 86. The same 89 and the AND gate 88 constitute a divide-by-8 circuit using the clock signal 33 as a clock. The AND gate 91 is a decoder for generating a clock simultaneously with the input signal 25, and the decode value can be arbitrarily selected.

D-FF93. By 97 and ORGATE 95.

The pulse width of the AND gate 91 is widened and the signal 35 is output. The signal 35 becomes a clock synchronized with the input signal 25.

FIG. 8 shows a timing chart showing the operation of FIG. 7.

In this example, when the length of the input signal 2501 bits is T, the period of the clock pulse of each circuit is T/8, but the period of the clock pulse may be arbitrary. Furthermore, the edge detected by the second edge detection circuit 26 may be a falling edge.

〔Effect of the invention〕

According to the present invention, it is possible to reproduce a clock that is synchronized with a signal after noise in the input digital signal has been removed, so that the error rate such as increase or decrease of the clock is reduced, and the error rate of the input digital signal is reduced.

Ru.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of an embodiment including the present invention, and Fig. fa2 is an explanation of an ideal signal and its falling edge detection output.
Figure 3 is an explanatory diagram of the falling edge detection output of a signal mixed with noise, Figure 4 is an explanatory diagram of the operation timing of Figure 3, and Figure 5 is a diagram of the first edge detection circuit including the present invention. A diagram showing a detailed embodiment of a counting circuit and a 71J cup flop circuit, FIG. 6 is a diagram showing a timing chart showing its operation, and FIG. 7 is a diagram showing a second edge detection circuit including the present invention.
FIG. 8 is a diagram showing a detailed embodiment of the second counting circuit and the start-stop type data synchronization circuit, and is an operation time chart thereof. 12...First edge detection circuit. 16...First counting circuit 24...Flip-flop circuit. 26...Second edge detection circuit. 29...Second counting circuit. 34... Start-stop data synchronization circuit. Horse 20 3rd Fertility '' Meng Bi (Gen & Washa 4-8n ~
Spear 8 Chaos 6e

Claims (1)

[Claims] In an asynchronous data synchronization circuit that receives a digital signal as input, a first edge detection circuit detects a falling edge and a rising edge of the digital signal, and a first edge detection circuit detects a falling edge and a rising edge of the digital signal; A first counting circuit detects that a certain period of time has elapsed after being reset by an edge, and a second edge detected next to the first edge detected by the first edge detection circuit A flip-flop circuit whose state changes according to the falling or rising edge of the first edge only when detected after the certain time period detected by the counting circuit No. 1, and an edge of the output of the flip-flop circuit. a second edge detection circuit for detecting;
a second counting circuit that counts an interval between a fourth edge detected by the second edge detection circuit and a fifth edge detected next to the fourth edge; 1. A data synchronization circuit characterized in that synchronization is achieved at a fifth edge only when an interval between the edge and the fifth edge is permissible in terms of format.