JPH0418485B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data synchronization circuit for synchronizing digital signals.

Digital signal synchronization methods include methods that use a tank circuit to synchronize data and PLL to reduce data capture errors due to signal jitter and dropouts. There are methods to generate rate signals. Furthermore, there is a method of achieving start-stop synchronization using a signal generated by the above method or a signal with a constant period. However, in the above method, when synchronization is attempted using input data, there is a drawback that dropouts in the data disturb the synchronization.

An object of the present invention is to provide a data synchronization circuit which eliminates the above-mentioned conventional drawbacks and which synchronizes only with edges at intervals permitted by the format of an input signal, thereby eliminating disturbances in data synchronization due to dropouts and the like. is to provide.

When capturing a digital signal, first a data strobe pulse synchronized with the signal is generated, and data is captured using this signal. The present invention relates to a method for generating data strobe pulses synchronized with this signal.

For this purpose, edges of the input signal are detected and synchronization is achieved using the edges. However, with this method, if the edge timing shifts due to a dropout in the signal, synchronization will be disrupted. In the present invention, in order to remove edges with shifted timing caused by dropouts, etc., only edges with timing allowed by the signal format are extracted,
Synchronization is attempted only at these extracted edges.

The present invention will be explained in detail using a specific example. FIG. 1 shows the configuration of a data synchronization circuit including the present invention. An edge detection circuit 2 generates an edge signal 3 from an input digital signal 1 . This edge signal 3 resets the counting circuit 5. This counting circuit 5 counts the signal 4 except for the above-mentioned reset synchronization. The output 6 of this counting circuit 5 is decoded by a decoder 7 to obtain a decoded output 8. This decoded output 8 is latched by a latch circuit 10 at the timing of a signal 9. This latch output 11 and the edge signal 3 are matched by an AND gate 12 to obtain a match output 13. A start-stop synchronous circuit 1 which uses this coincidence output 13 as a signal 14 as a clock pulse
5 synchronization signal, data strobe pulse 16
generate.

Next, the present invention will be explained in more detail with reference to the time chart shown in FIG. In input digital signal 1, the broken line is the normal edge, and this is an example where the edge is shifted due to noise or the like. When the edge interval T in the same signal is normal, T≠T'≠T''. Edge output 3 is obtained for such a signal. Decoder output 8 of the counter that is reset at edge output 3 is shown. .The latch output 11 of the decoder output 8 is shown.
A coincidence output 13 between the latch output 11 and edge output 3 is shown. This coincidence output 13 is a wedge signal with a normal interval, and by synchronizing the harmonic synchronization circuit 15 with this signal, it is possible to avoid erroneous synchronization due to noise or the like. Here, the decoded value of the decoder 7 is, for example, one clock shorter than the normal edge interval, and is in phase with the edge signal of the normal interval at the latch circuit output 11.

Next, the edge detection circuit 2 will be explained in more detail with reference to the circuit diagram of FIG. The basic configuration of the edge detection circuit 2 is shown in FIG. 3b. Input digital signal 1 is delayed by delay circuit 22, and this delayed output 2
3 and input digital signal 1 to the E-OR circuit 18.
The output 3 becomes the edge signal. Here, the edge signal width is determined by the delay time of the delay circuit 22. As this delay circuit 22, a delay element such as a delay line, a shift register, or the like is used. A method using this shift register is shown in FIG. 3a.

The input digital signal 1 is input to the first stage D-FF 17, and the same output 19 is input to the second stage D-FF 17 to obtain the same output 20. Both outputs 19 and 20 are
- It is input to the OR circuit 18 and produces edge output 3. Here, the width of edge output 3 is D-FF17
is equal to the period of the clock pulse 21. By making the clock pulse 21 equal to the signal 4 of the counting circuit 5 and the signal 9 of the latch circuit 10, both input signals 3 and 11 can be synchronized by the AND gate 12.

As described above, according to the present invention, since the edge interval is gated by the counter, it is possible to easily configure a relatively long edge interval. In addition, in order to gate the edge interval, the edge interval is generated by setting a decode value of one clock or more and shifting the same value by one bit, without having to provide two systems of the counter itself and with a strict timing margin. , it becomes possible to sequentially count the edge intervals and match the same edge. Furthermore, by changing the decode value, it is possible to extract multiple edge intervals and set the edge extraction range.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data synchronization circuit according to the present invention, FIG. 2 is a time chart showing the operation of the embodiment, and FIG. 3 is a circuit diagram showing an embodiment of an edge detection circuit. 2: Edge detection circuit, 3: Counting circuit.

Claims (1)

[Claims] 1. In a data synchronization circuit that reproduces a clock synchronized with an input digital signal, there is an edge detection circuit that detects the edge of the digital signal, and a first circuit that counts the interval between the output signals of the edge detection circuit. a counting circuit, a decoder circuit to which the output signal of the first counting circuit is supplied and which extracts a specific count value indicating that the edge interval of the input digital signal is a predetermined interval determined by the transmission rate; A matching circuit detects the match between the output signal of the decoder circuit and the output signal of the edge detection circuit, and a second matching circuit that is set to an initial state by the output signal of this matching circuit and generates a clock synchronized with the input digital signal. A data synchronization circuit comprising a counting circuit.