JPH0415649B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When capturing a digital signal, a data strobe pulse synchronized with the signal is generated, and data is captured using the pulse. The present invention relates to a data synchronization circuit that generates strobe pulses synchronized with this signal.

There is a method of using edges of an input digital signal as a phase synchronization signal for an asynchronous synchronization circuit, but synchronization will be disrupted if an edge that has been disturbed by a dropout in the data or the like is used.

Therefore, we have developed an effective method of counting the intervals between rising and falling edges, as well as between falling and rising edges, and synchronizing using only edges of an allowable length in order to eliminate edges that have experienced disturbance. I applied.

If subsequent studies show that there are differences in the transfer characteristics of the falling and rising edges of the input digital signal due to the transfer characteristics of the transmission system and the characteristics of the signal acquisition circuit, the following problems will occur.

This problem will be explained in detail using the time chart shown in FIG.

a is a recording signal pattern, and b is an example of its reproduced output signal pattern. Here, when data slicing b, the optimal comparison level is
Suppose that there are cases where e is set to e ₁ , e is set to e ₂ , and e is set to e ₃ .

First, in the case of e ₁ , the positive pattern is contracted and the negative pattern is expanded [the output is shown in (c)]. ].
In the case of _e2 , the slice level is optimal, and its output d matches the recording signal a. Next, in e ₃ when the slice level falls below the reference level,
The output is e, where the positive pattern is expanded and the negative pattern is contracted, resulting in an error.

On the other hand, a similar problem occurs when the rise time and fall time are different due to the characteristics of the comparator. An example of this is f, where when slicing at the _e2 level, the fall time is longer than the rise time. As a result, the edge timing is shifted. In the above case, the above method of extracting a phase synchronization signal by counting the interval between rising and falling edges and the interval between falling and rising edges reduces the number of extractions, resulting in a decrease in jitter margin,
There were cases where synchronization was not possible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data synchronization circuit that does not perform synchronization at edges that have been subjected to disturbances, and is capable of synchronization even if slice level fluctuations or differences in comparator characteristics occur.

Therefore, in the present invention, by detecting only one of the rising edge and the falling edge of the input signal, even if the above-mentioned timing deviation from the rising edge to the falling edge occurs, the timing from the rising edge to the falling edge is detected as the first edge.
As you can see from the figure, there is no timing shift.

By counting the time interval of one edge, extracting an edge with a timing that is permissible in the signal format, and performing synchronization using only this extracted edge, the edge that has been subjected to disturbance can be removed.

The present invention will be explained in detail using specific examples.

FIG. 2 shows the principle of the configuration of a data synchronization circuit including the present invention.

2 is a falling edge detection circuit, for example,
The delay means and logic circuit output edge signal 3a at the falling edge of input digital signal 1. The counting circuit 5 is cleared by this falling edge signal 3. This counting circuit 5 counts the signal 4 except for the above-mentioned clearing time. The output 6 of this counting circuit 5 is decoded by a decoder 7 to obtain a decoded output 8. This decoded output 8 is latched by a latch circuit 10 at the timing of a signal 9. This latch output 11 and the rising edge signal 3 are
The AND gate 12 makes a match, and a match output 13 is obtained. This coincidence output 13 is used as a phase synchronization signal for an asynchronous synchronization circuit 15 which uses a signal 14 as a clock pulse, and a data strobe pulse 16 is generated.

Next, the operation shown in FIG. 2 will be explained in detail with reference to the time chart shown in FIG. It is assumed that the input digital signal 1 is a continuous pulse with a period of T, and there is a timing shift between edges A and B.

For this signal, a falling edge 3 is obtained. 8, which is the decoded output of the counting circuit 5 which was reset at the falling edge 3, and an output 11, which is obtained by latching 8, are shown. 11 is set so that it is at a time nT (n1, n are integers; the same applies hereinafter) from the reset time and has a width _Tw . The coincidence output between this latch output 11 and the falling edge 3 is 13.

Here, the normal falling edge signal of C following B is also blocked, so the circuit that prevents this is the fourth
It is a diagram.

FIG. 4 shows an example of an asynchronous synchronous circuit 1 added to the circuit shown in FIG.
a decoder 18 which decodes the output 17 of 5 and obtains the decoded output 19; and an OR gate 2 which obtains the OR output 21 of the decoded output 8 and the decoded output 19.
0 is added. Therefore the coincidence output 13
is obtained by ANDing the falling edge signal 3 and the latch output 11 obtained by latching the OR output 21 with the signal 9.

FIG. 5 shows the time chart of FIG. 4 to explain its operation. The input digital signal is the same as in FIG.

Similarly to FIG. 2, the decode output 8 is set so that the latch output 11 of T _w width is obtained nT after the time when the counting circuit 5 is cleared. On the other hand, since the decoded output 19 is the decoded value of the asynchronous synchronization circuit 15 whose phase is synchronized by the coincidence output 13,
After nT, a pulse of width T _G can be output.

The output 11 obtained by ORing the decoded outputs 8 and 19 and latching it is shown. Therefore, the signal of the falling edge C following the abnormal edge B will be passed as a phase synchronized signal.

Furthermore, a circuit for extracting as a phase synchronization signal a rising edge that does not disturb the phase of a phase synchronized with a normal falling edge is shown in FIG. 6 and will be described.

FIG. 6 is a diagram with the following additions to FIG. 4. That is, 1 to 21 are the same as those shown in FIG.
Latch circuit 2 which latches and obtains latch output 25
4. AND gate 2 to obtain a coincidence output 27 between the latch output 25 and the rising edge signal 23;
6. An OR gate 28 which takes an OR between the coincidence output 27 and the coincidence output 13 to obtain a phase synchronization signal 29.

This time chart is shown in FIG. 7 and will be explained in detail. Input digital signal 1 shows a rising edge signal 23, which is a signal similar to that described above. The match output 13 and decode output 19, which have already been explained, are shown. The output 25 obtained by latching the decode output 19 is shown. As mentioned above, the latch output 25 becomes a pulse of T _G width nT after the phase synchronization signal, so the output 27 coincides with the rising edge signal 23.
get. The OR output 29 of the coincidence output 27 and the coincidence output 13 becomes a phase synchronization signal.

Note that the rising edge signal 3 in FIGS. 2 and 4 may be replaced with the rising edge, and the falling edge signal 3 and the rising edge signal 23 in FIG. 6 may be replaced with each other.

According to the present invention, when edges are extracted by counting the intervals between falling edges, rising edges, or rising edges and falling edges, the extraction rate is reduced due to slice level fluctuations and differences in comparator characteristics. In the present invention, using either one of , falling edge, and rising edge,
Stable synchronization is possible without fluctuations in the extraction rate. As a result, synchronization can be achieved without being disturbed by edges caused by disturbances, and without depending on slice level fluctuations or differences in comparator characteristics. Furthermore, since the extraction rate does not decrease, a jitter tracking margin for the data strobe clock is secured.

Also, rising from falling, or
In the method of extracting edges by counting the interval between rising and falling edges, for example, the edges move as shown in Figure 7, and the lengths of A and B are exactly T.
In this case, the edge cannot be removed, but in the present invention, it can be removed.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the transfer characteristics, Fig. 2 is a configuration diagram of an embodiment of a data synchronization circuit that measures falling edge intervals and achieves phase synchronization, Fig. 3 is its time chart, and Fig. 4 The figure is a block diagram of an embodiment of a data synchronization circuit that extracts normal rising edges that were not extracted in Figure 2 and achieves phase synchronization, Figure 5 is a time chart thereof, and Figure 6 is the fourth FIG. 7 is a block diagram of an embodiment of a data synchronization circuit which extracts even the falling edge of a normal phase from the phase synchronization signal shown in the figure and achieves phase synchronization, and FIG. 7 is a time chart thereof. 1... Input digital signal, 2... Rising edge detection circuit, 22... Rising edge detection circuit, 5... Counting circuit, 15... Start-stop type synchronous circuit.

Claims (1)

[Claims] 1. An edge detection circuit that detects the rising (or falling) edge of the digital signal in a data synchronization circuit that reproduces a clock synchronized with the input digital signal, and an edge detection circuit that detects the rising (or falling) edge of the digital signal, and the rising edge of the output signal of the edge detection circuit. (or falling) edge interval counting circuit;
A first decoder circuit is supplied with the output signal of this counting circuit and extracts a specific count value indicating that the interval between rising (or falling) edges of the input digital signal is a predetermined interval determined by the transmission rate. a logical sum means which receives the output signal of the first decoder circuit as one input; a matching circuit which detects a match between the output of the logical sum means and the output signal of the edge detection circuit; An asynchronous synchronous circuit that is set to an initial state by the output signal and generates a clock synchronized with the input digital signal, and an output signal of this asynchronous synchronous circuit is supplied, and the rising (or falling) edge of the input digital signal and a second decoder circuit that extracts a specific count value indicating that the interval is a predetermined interval determined by the transmission rate, and the output of the second decoder circuit is used as the other input of the logical sum means. A data synchronization circuit characterized by: