JPH0738535A - Noise removing circuit - Google Patents

Abstract

PURPOSE:To provide a noise reduction circuit which can reduce error caused by single noise generated on a data line at the time of asynchronous data transmission. CONSTITUTION:This circuit is provided with an FF 1 to be turned off by the rising of a clock when input data are zero, to be, turned on by the rising of the clock when the single noise is generated during this OFF and to be turned off by the rising of the next clock, FF 2 to be turned off by the ON of the FF 1 caused by the generation of the single noise and to be turned on by the OFF of the FF 1, FF 3 to be cleared by the outputs of the FF 1 and FF 2 and the output of an exclusive OR, to divide a frequency with the falling of the clock and to generate a sampling clock with that output, and FF 4 to synchronously extract the output of the FF 1 with the sampling clock and to input it to a demodulation circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise elimination circuit in an asynchronous serial code transmission system.

[0002]

2. Description of the Related Art A demodulation circuit for receiving serial code data in a receiver
When demodulating at 10, what is commonly used is what is called an asynchronous transmission method, which is shown in FIG. 4 as an example. In this example, the operation when the clock is 16 times the data is shown in FIG. A start bit is sent before sending data, and a stop bit is sent after sending the data. When the start bit falls, the sampling counter is reset and counting is started. Data is demodulated by reading the data when the value of the sampling counter reaches 8.

[0003]

By the way, in the conventional case, there is a problem that erroneous information is read when a sporadic noise occurs on a data line during asynchronous data transmission.

Therefore, an object of the present invention is to solve the above-mentioned conventional problems and to provide a noise removing circuit capable of removing an error due to a single noise.

[0005]

In order to achieve the above object, the noise removing circuit 20 of the present invention is installed on the data input side of the demodulating circuit 10 provided in the asynchronous serial code transmission system as shown in FIGS. Has been done. The noise removal circuit 20
When the input data is zero, the D-type flip-flop (hereinafter referred to as FF) is turned off by the rising edge of the clock, and when a single noise occurs when this input is turned on, is turned on by the rising edge of the clock and is turned off by the rising edge of the next clock. 1 and FF1, which is turned off by the generation of a single noise of FF1 and is turned on by the turning off of FF1, is cleared by the outputs of FF1 and FF2 and the output of the exclusive OR, and is divided by the falling edge of the clock. It has an FF3 that circulates and generates a sampling clock with its output, and an FF4 that outputs the output of FF1 in synchronization with the sampling clock and inputs it to the demodulation circuit 10. In FIG. 2, IV is an inverter, and by inverting the clock,
It operates half a cycle earlier to operate stably.

[0006]

The operation will be described with reference to the operation timing shown in FIG. When a single noise occurs in the input data, the FF1 is turned on and inverted at the rising edge of the clock. Since there is no noise at the next rising edge of the clock, the FF1 is inverted to the original OFF state. On the other hand, FF2 is turned off, turned on, and turned off. FF1 between these two clocks
And FF2 do not match, the output exclusive or (EOR) of FF1 and FF2 becomes 1, the output of FF3 is cleared and the sampling clock of FF4 becomes 0, and FF4 becomes FF1 due to noise.
Since the output of is not read, noise can be removed without being read. However, the detection time at the sampling clock is a delay time, but this is not a problem time in general.

[0007]

EXAMPLE FIG. 3 shows a case without noise and a case with noise separately. That is, the operation timing in a normal state in which no noise is added to the input data is shown in the upper half without noise. The clock here is an example of a clock 16 times faster than 1 bit. The output A of the FF1 in which the input data is turned off is inverted to off at the rising edge of the clock and continues to be in the off state, and the output B of the FF2 remains on. FF2 at the next clock rise
Output B of is inverted to off and continues to be off. Time S
During this period, the output A of FF1 is off and the output B of FF2 is on, so the output of the exclusive OR (EOR) of outputs A and B is 1, and FF3 is cleared and the sampling clock of the output is 0. , It is inverted at the next falling edge of the clock that is no longer cleared, and the sampling clock is generated.

The sampling clock has a frequency half that of the clock. The FF4 synchronizes the output of the FF1 with the sampling clock, becomes the output of the noise removal circuit 20, and inputs it to the demodulation circuit 10. 0 to 1 at the end of the start bit
When FF1 and FF2 rise, FF1 rises first and FF2 rises with a delay of one clock.
Output becomes inconsistent and the sampling clock becomes 0, but at the next rising edge of the sampling clock, FF
4 turns on the output.

The operation timing when noise is added to the input data is shown in the lower half with noise. That is,
This is an example in which noise A at the beginning of the start bit 0, noise B at the middle of the start bit 0, noise C at the beginning of the first bit, and noise D at the middle thereof on the minus side are included in the input data. When the input data becomes 0 at the start bit, the output A of FF1 is inverted OFF, the output B of FF2 remains ON, the output of both exclusive OR (EOR) becomes 1, and when noise A enters at the next clock, F
As a result, F1 is turned on inversion and FF2 is turned off by turning off FF1 before that, and FF1 and F
The outputs of F2 do not match and the exclusive OR (E
The output of OR) is 1. Next, FF1 becomes inversion off and FF2 becomes inversion on because the noise disappears, and it becomes off at the next clock rise, and the outputs of FF1 and FF2 do not match for 2 clocks, and the output of exclusive OR (EOR) It becomes 1 and the sampling clock becomes 0 during that time, and even if noise enters, it is not accepted, and thereafter, the sampling clock is normally generated and the FF 4 normally outputs the data.

Next, when noise B is added to the input data when sampling is performed at the eighth clock, FF1 is turned on by the rise of noise and FF1 is turned off by the fall of noise. FF2 follows 1
Since it turns on and off with a clock delay, the outputs of FF1 and FF2 do not match for two clocks during that time, FF3 is cleared and its output sampling clock becomes 0, and the output of FF4 receives no noise from the input data. Remove and output regular data. Similarly, in the case of noise C and noise D, noise is not received and noise is removed to output normal data.

[0011]

Since the present invention is constructed as described above, it is possible to directly eliminate the error due to the single noise. In addition, the circuit is simple, economical, and easy to maintain, which is an excellent effect. Also,
It is also effective for a method of detecting a change and transmitting a code, such as NRZI code transmission.

[Brief description of drawings]

FIG. 1 is a schematic diagram of an asynchronous serial code transmission system in which a noise removing circuit of the present invention is installed.

FIG. 2 is a block diagram of a noise removing circuit.

FIG. 3 is an operation explanatory diagram of the above.

FIG. 4 is a schematic diagram of a conventionally known asynchronous serial code transmission system.

FIG. 5 is an operation explanatory diagram of the above.

[Explanation of symbols]

 10 Demodulation circuit 20 Noise removal circuit

Claims (1)

[Claims] 1. A data input side of a demodulation circuit provided in an asynchronous serial code transmission system, which is turned off by a rising edge of a clock when input data is zero, and when a single noise occurs when the input data is off, a clock signal is generated. D-type flip-flop (1) which is turned on at the rising edge and turned off at the next rising edge of the clock, and D
Type flip-flop (1) is turned off by the generation of the one-time noise, and the flip-flop is also turned on.
D-type flip-flop turned on by turning off (1) (2)
And the output of the D-type flip-flop (1) and the D-type flip-flop (2) and the output of the exclusive OR, and the D-type flip-flop that divides at the falling edge of the clock and generates the sampling clock at the output (3) and a D-type flip-flop (4) that outputs the output of the D-type flip-flop (1) in synchronization with the sampling clock and inputs the output to the demodulation circuit. .