JPH0542070B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to signal reproduction of a compact disc, and relates to a signal synchronization circuit at the time of signal acquisition.

[Background of the invention]

As described in Japanese Patent Application Laid-Open No. 58-64841, the conventional signal synchronization circuit detects the last level inversion position of the synchronization signal area of a compact disk type digital signal as shown in FIG. Figure b,
This was to be the start time of importing the data area. However, no consideration was given to the fact that if the last level inversion position in the synchronization signal area moves due to jitter or dropout, a data capture error may occur.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal synchronization circuit that allows data acquisition to be started at the intended timing even if the last level inversion position of the block synchronization signal is moved.

[Summary of the invention]

The main point of the present invention is that the input digital signal "1",
By using the bit synchronization signal that determines "0", the block synchronization signal of the input digital signal is detected by pattern matching, and the signal that is within the range of the time gate described later is set as the start time of data acquisition. , is reset by the signal detected by the pattern match, counts the length of one block of the input digital signal by the bit synchronization signal, and starts counting at the end of counting, that is, at the time when the next block synchronization signal is to be detected. A counting circuit that outputs an output is provided, and the output of the counting circuit is also used as the start time of data acquisition.

Here, when the period of the signal detected by a fixed clock is Tb, which is the length of one block of the input digital signal, extract only the block synchronization signal when the period is Tb±ΔT, and When the sync signal is lost, supplement the sync signal,
A synchronization signal protection circuit for outputting a protection synchronization signal is provided, and the output of the synchronization signal protection circuit is positioned approximately in the middle of the block synchronization signal region of the input digital signal to obtain the above-mentioned time gate signal.

Furthermore, when the synchronization signal protection circuit detects that the block synchronization signal is missing over consecutive p blocks, the position of the protection synchronization signal, that is, the time gate signal, is stabilized at the position where the block synchronization signal should originally be. Since it takes time to complete the process, the signal in which the block synchronization signal is detected by the above-mentioned pattern matching is unconditionally set as the start time of the above-mentioned data acquisition.

[Embodiments of the invention]

The present invention will be explained using a specific example in which it is used in a compact disc (hereinafter abbreviated as CD) type digital audio disc player.

As shown in Figure 2a, in the data array of the CD method, when the unit length is T, one block is
It is 588T long and has a 24T synchronization signal area at the beginning. The 24T synchronization signal area includes the preceding 11T, subsequent 11T, and
Finally, it is composed of 2T patterns with mutually inverted levels. Since the CD system uses the NRZ-I modulation type, the synchronization signal pattern may have a level completely opposite to that shown in FIG.

FIG. 1 shows a configuration diagram of an embodiment of the present invention and will be described.

The bit synchronization circuit 2 extracts level change points, that is, edges, of the input digital signal 1, and generates a bit synchronization signal 3 whose phase is synchronized with the input digital signal 1 using the edges. Here, as the phase synchronization method, there are a method using a PLL, a method using a start-stop synchronization circuit, etc.

The shift digital 6 determines whether the input digital signal 1 is "1" or "0" based on the bit synchronization signal 3, and
Import sequentially. The number of stages of the shift register 6 is at least equal to the number of constituent bits required for extracting the synchronization signal.

The first synchronization signal detection circuit 13 detects the synchronization signal pattern of the input digital signal 1 using the output signal 12 of the oscillation circuit 11 as a clock, and outputs a first detected synchronization signal 14. The synchronization signal protection circuit 15, which also operates using the signal 12 as a clock, is the first
The first detection synchronization signal 14 is input, and the period of the first detection synchronization signal 14 is the original length of one block.
For example, when the first detection synchronization signal 14 in the range of 588T±16T is detected for q blocks consecutively with respect to 588T, the synchronization loss signal 16 is set to "L" and the time t ₁ when rT has elapsed from that point. The protection synchronization signal 17 is output to. In addition, if the first detection synchronization signal 14 is not detected within the next 588T±16T from the time when the above-mentioned q blocks are continuously detected, the protection synchronization signal 14 is detected after 588T from the above-mentioned time _t1 . Outputs 17. Furthermore, if the first detection synchronization signal is not detected within the range of 588T±16T for p blocks consecutively, the period of the protection synchronization signal 17 is set to be constant at 588T, and the synchronization loss signal 1
6 to “H”. Here, p, q, and r are arbitrary integers, and r is selected so as to be located at a time approximately in the middle of the synchronization signal region to be detected next.

Next, the protection synchronization signal 17 sets the RS flip-flop 20, and the protection synchronization signal 17 is applied to the delay circuit 1.
The RS flip-flop 20 is reset by the signal 19 delayed by a predetermined time at 8, and a time gate signal 21 is obtained at the output of the RS flip-flop 20.

The second synchronization signal detection circuit 8 outputs a second detected synchronization signal 9 when the parallel output 7 of the shift register matches the synchronization signal pattern. The delay time of the delay circuit 18 is selected so that the second detection synchronization signal is output at an intermediate position of the time gate signal 21.

When the first detected synchronization signal 14 is missing p blocks consecutively, the output signal 23 of the inverter circuit 22 which receives the synchronization loss signal 16 as input is Since it becomes “L” level, the second detection synchronization signal 9
is selected by the AND gate circuit 24, passes through the OR gate circuit 28, is output as a data acquisition reference signal 29, resets the counting circuit 4, and is input to the data acquisition circuit 10.

Next, the synchronization loss signal 16 is at "L" level, that is,
When the first detection synchronization signal 14 is continuously detected, the output signal 2 of the inverter circuit 22
3 becomes "H", the second detection synchronization signal during the "H" period of the time gate signal 21 is output as the reference signal 29 for data acquisition. That is, the second detection synchronization signal 9 detected in the data area due to jitter or dropout can be excluded, and only the second detection synchronization signal 9 located at the correct position can be extracted as the reference signal 29.

The counting circuit 4 is reset by the reference signal 29 and outputs the counting signal 5 at the time when 588 bit synchronization signals 3 are counted, that is, at the time when the next reference signal 29 is to be output after the reference signal 29 is output. Therefore, for example, when the synchronization loss signal 16 is "L", even if the second detected synchronization signal 9 is not output during the "H" period of the time gate signal 21, the second supplementary synchronization signal 5 is output from the OR gate. A reference signal 29 can be obtained through the circuit 28 .

The data acquisition circuit 10 uses the reference signal 29
Starting from , the bit synchronization signals 3 can be counted and the parallel output signals 7 of the shift register 6 can be sequentially taken in.

From FIG. 4 onwards, timing chart diagrams showing the operation of the configuration diagram of FIG. 1 will be shown and explained in more detail.

FIG. 4 shows the operation of the second synchronization detection circuit 8. A shift register 6 takes in data using a bit synchronization signal 3 generated by a bit synchronization circuit 2 in phase synchronization with the input digital signal 1. In this example, since the falling edge of the bit synchronization signal 3 is phase-synchronized with the input digital signal 1, the shift register 6 transfers the input digital signal 1 to the input digital signal 1 at the rising edge of the bit synchronization signal 3.
Import as -1. 6-2 in the same figure is obtained by further shifting 6-1 in the same figure. From 6-1 and 6-2, the edge of the input digital signal 1 is detected, that is, the edge is set to "1" and "0" by the bit synchronization signal 3. ” and is shifted by the synchronization signal pattern 24T, and the second synchronization signal detection circuit 8 obtains a second detected synchronization signal 9 which is a coincidence output.

FIG. 5 shows an example of the operation of the first synchronization signal detection circuit 13. The input digital signal 1 is shifted by the output 12 of the oscillation circuit 11 as shown in FIG. 13-1 and 13-2. If the period of the output 12 of the oscillation circuit 11 is selected to be 1/8 of the unit length T of the input digital signal, then
In order to detect the synchronization signal by pattern matching as in the second synchronization signal detection circuit, a shift register with 88 stages or more is required, which increases the circuit scale. , 13-2, the level change points, that is, edges of the input digital signal are detected as shown in FIG.
In the case of 3 clocks, the result shown in FIG. 13-4 is obtained. Furthermore, when the same figure 13-4 is detected continuously,
That is, when the synchronization signal of the input digital signal is detected, the first detected synchronization signal 14 is obtained.

Next, the operation of the synchronizing signal protection circuit 15 will be explained with reference to FIG. To make the explanation easier to understand, the sixth
It is assumed that the missing signal 16 is "H" at time 30 in the figure. At time 31 in the figure, the synchronization signal of the input digital signal 1 is detected as the first detected synchronization signal 14.
Next, the position where the synchronization signal is to be detected, that is, the interval from time 31 to, for example, 588T±16T, time 3 in the same figure.
2 to time 34, the time window signal 15-1
Since the first detection synchronization signal 14 is detected at time 33 when the first detection synchronization signal is opened, the period of the first detection synchronization signal is
A signal 15-2 is obtained as the first detected synchronization signal satisfying 588T±16T. Next, time window signal 15-
The time when 1 should open is the time 33 when signal 15-2 is obtained.
It is a section 588T±16T away from the time 37'
Time window signal 15-1 by 32T from (not shown)
open. In this way, the synchronization signal that appears in the data area, for example at time 36 in FIG.
It does not appear on signal 15-2.

Returning the explanation to time 33, at time 33, the first
Since the signal 15-2 in which the period of the detection synchronization signal 14 satisfied 588T±16 was detected, the synchronization loss signal 16 is set to "L" at time 35, and the protection synchronization signal is output at time 37, which is 577T away from time 33, for example. Outputs 17.

Next, a case where the synchronization signal is lost will be explained. The time at which the time window signal 15-1 should open after time 39' (not shown) and time 40 in FIG. 6 is as follows:
From time 38 when the last synchronization signal was detected (588
×2) Time 41′ (not shown) separated by T±16,
This is the time 43 section. Moreover, the protection synchronization signal 17 is
From time 38 when the last synchronization signal 14 was detected
After outputting at time 39, which is 577T away, synchronization signal is not detected at time 39' and time 40, so time 3
It is output at time 41, which is 588T away from 9.

Furthermore, a case where synchronization signals are continuously lost will be explained. After the synchronization signal is detected at time 42 in FIG. 6, the synchronization signal is detected continuously over two blocks in this example at time 44' (not shown), time 45 interval, time 46' (not shown), and time 47 interval. Therefore, the synchronization loss signal 16 is set to "H" at time 48. At this time, the protection synchronization signal 17 is output at time 44, which is 577T away from time 42 when the last synchronization signal was detected, and then 588T from time 44.
It is output at a distant time 46, and the synchronization signal is not detected even at time 47, so 588T is output from time 46.
After the distant time 49, the cycle is kept constant at 588T, and the next two blocks are output in succession until the synchronization signal is output.

In addition, in FIG. 6, the output signal 19 obtained by delaying the protection synchronization signal 17 by the delay circuit 18, and
Also shown is a time gate signal 21 which is the output of a flip-flop 20 which is set at 7 and reset at signal 19.

Next, the overall operation of FIG. 1 will be explained with reference to FIG. Again, to simplify the explanation, it is assumed that the missing signal 16 is "H" at time 50. As explained in FIG. 6, the first
The detection synchronization signal 14 is detected, and the synchronization loss signal 1 is detected.
6 to “L” at time 53, and from time 52 to 577T
As a result of outputting the protection synchronization signal 17 at the elapsed time 54, the time gate signal 21 is output at time 54 and time 5.
Obtained in 6 sections. Since the second detection synchronization signal 9 is detected at time 55, the reference signal 29 is obtained and the counting circuit 4 is reset.

Next, in the interval between time 57 and time 59 when the synchronization signal is lost, the second detected synchronization signal 9 is not output, but since the counting circuit 4 was reset with the reference signal 27 at the previous time 55, The count value signal 5 that counts and outputs 588 bit synchronization signals 3 is at time 5.
Since the reference signal 29 is also obtained at time 58, the counting circuit 4 is reset and the data acquisition circuit 10 is output at time 58.
Data can be correctly captured using the reference signal 29 as a starting point.

Furthermore, if the synchronization signal is missing, as in the previous case, since the counting circuit 4 is reset with the reference signal 29 at time 58, the counting circuit 4 is reset at time 60 when the second detected synchronization signal 9 should originally be present. Since it is outputting the count value signal 5, the reference signal 29 is also obtained at time 60 to reset the counting circuit 4, and the reference signal 29 causes the data capture circuit to correctly capture data.

Since two consecutive blocks of synchronization signals are lost, the synchronization signal protection circuit 15 sets the synchronization loss signal 16 to "H" at time 61.

Time 6 during the period in which this synchronization loss signal 16 is “H”
2 and time 63 are detected by the AND circuit 24 regardless of the output of the time gate signal 21.
is selected, the reference signal 29 is obtained, the counting circuit is reset, and the data capture circuit 10 can correctly capture data using the reference signal 29 as a starting point.

〔Effect of the invention〕

According to the present invention, the data acquisition start signal can be correctly reproduced even when the synchronization signal is missing, so it is possible to reduce burst errors such as erroneous data acquisition start times and errors in one entire block. .

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of an embodiment of the present invention, Fig. 2 is a waveform diagram for explaining the data series of the input digital signal and the conventional one, Fig. 3 is a synchronization signal pattern diagram, and Fig. 4 is a diagram of the second embodiment. 5 is a time chart diagram showing an example of the operation of the first synchronization signal detection circuit. FIG. 6 is a time chart diagram showing an example of the operation of the synchronization protection circuit. 7 is a time chart showing an example of the overall operation of FIG. 1. 1... Input digital signal, 3... Bit synchronization signal, 13... First synchronization signal detection circuit, 15...
Synchronization signal protection circuit, 8... second synchronization signal detection circuit.

Claims (1)

[Claims] 1. In a data acquisition circuit in which one block consists of m data words with a block synchronization signal at the beginning, and data is acquired from digital signals that are sequentially input in block units, a master signal generated by a crystal oscillator, etc. a first synchronization signal detection circuit that detects the block synchronization signal as a first synchronization signal from the digital signal using a clock; and a first synchronization signal detection circuit that detects the block synchronization signal from the digital signal as a first synchronization signal; a second synchronization signal detection circuit that detects the block synchronization signal detected by pattern matching from the second synchronization signal as a second synchronization signal; a counting circuit that outputs a counting output for each length of m data words; the output of the first synchronizing signal detection circuit and the master clock are input; the missing of the first synchronizing signal is monitored p times consecutively; When the first synchronization signal is detected to be missing, it becomes the first state. When the first synchronization signal is detected q times in succession, it becomes the second state. A signal starts counting by the master clock, outputs a first time window with a preset time width at a location including after the length of the m data words, and the first synchronization signal is within the first time window. If the first synchronization signal is output within the first time window, the master clock counts from that point as a starting point and calculates the length of the m data words. A protection synchronization signal is output at a position obtained by subtracting a time shorter than the time width of the first time window from The protection synchronization signal is counted by the master clock, and the m
a protection circuit that outputs a protection synchronization signal at a position after a data word length of using two signals in a second time window that appear within the second time window while the missing signal is in the second state and the first synchronization signal is detected. the second synchronization signal, the counting output when the missing signal is in the second state and the first synchronization signal is missing, and the second synchronization signal when the missing signal is in the first state. 1. A signal synchronization circuit comprising: a selection circuit for selectively outputting a signal, wherein outputs of the selection circuit are a reset signal for the counting circuit and a capture start reference signal for capturing data from the digital signal.