JPS6316935B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PM code reproducing device that reproduces signals only by logical operations in a partially synchronous transmission system using PM codes.

In partially synchronous signal transmission between information processing devices, in addition to the parallel transmission method, a serial transmission method in which parallel signals are converted into serial signals by multiplexing and transmitted is also widely used. In the serial transmission system, a clock necessary for signal identification on the receiving side is transmitted together with data, but a self-clock code that has both data and clock is normally used as a transmission code. Although various codes are used as self-clock codes, PM (Phase Modulation) code is one of the codes with abundant clock signal components.
PM code divides NRZ (Non Return to Zero) code data into two bits per bit, converting “1” to “01”.
(or “10”), or “0” converted to “10” (or “01”).

A signal reproducing circuit in a conventional transmission system using PM codes was configured as shown in FIG. That is, the received signal is waveform-shaped by an amplifier circuit or the like and then inputted to the signal input terminal 1, and from there is supplied to the data input terminals of the one-shot circuit 2 and the data discrimination circuit 3. The output terminal of the one shot circuit 2 is connected to the input terminal of a phase comparator 4, and the output signal of the phase comparator 4 is inputted to a voltage controlled oscillator 6 after passing through a low pass filter 5. The output terminal of the voltage controlled oscillator 6 is connected to the other input terminal of the phase comparator 4 and the input terminal of the frequency dividing circuit 7. The output terminal of the frequency dividing circuit 7 is connected to the clock input terminal and the clock output terminal 9 of the data discrimination circuit 3, and the output signal of the data discrimination circuit 3 is supplied to the data output terminal 11. phase comparator 4,
The low-pass filter 5 and the voltage-controlled oscillator 6 constitute a phase-locked loop, a so-called PLL (Phase Locked Loop) circuit 12.

Further, FIG. 2 shows an example of the signal waveform in the main part of FIG. This is the data to be output.

Next, the operation in this conventional example will be explained. The rise of input signal a by one-shot circuit 2,
Each pulse corresponding to a falling edge is generated and input to the phase comparator 4. The PLL circuit 12 generates a signal whose phase is almost synchronized with the rising and falling edges of the input signal a, which is divided into two by the frequency dividing circuit 7.
Clock b is obtained by dividing the frequency by a factor of 1. The data discrimination circuit 3 discriminates data by logical operation using input signal a and clock b. In the PLL circuit 12, the input signal a is first detected by the phase comparator 4.
The frequency and phase of the voltage controlled oscillator 6 are compared with the oscillation frequency and phase of the voltage controlled oscillator 6, and a voltage proportional to the error is generated. This error voltage is applied to the low-pass filter 5.
is applied to the control terminal of the voltage controlled oscillator 6 through the input signal, and changes the oscillation frequency in a direction that reduces the oscillation frequency difference and phase difference between the input signal and the voltage controlled oscillator 6. As a result, the voltage controlled oscillator 6 is drawn in by the input signal, and the oscillation frequency is stabilized.

As described above, in the conventional PM code reproducing circuit, since clock extraction is performed using the PLL circuit 12 having a feedback loop, it takes a certain amount of time to obtain a clock with stable frequency and phase. Therefore, when transmitting data, it is necessary to add a certain pattern of several tens to hundreds of bits, such as all "1"s, to the beginning for synchronization pull-in. For this reason, the data delay time due to the addition of the synchronization pull-in pattern significantly increases the processing time of the information processing device, and the circuit is complicated and expensive.

The present invention is intended to eliminate such drawbacks, and is characterized in that a clock and data are regenerated from a waveform-shaped received signal using a combination of logic gates and delay lines, and its purpose is to eliminate the need for a synchronization pull-in pattern. The purpose of this invention is to improve processing time and simplify the circuit.

FIG. 3 shows an embodiment of the invention. After the output signal is waveform-shaped by an amplifier circuit or the like, it is input to the signal input terminal 1, and further supplied to the input terminals of the inverter 13, the And gate 14, and the Ex-Or gate 15. The output terminal of inverter 13 is And gate 1
6, connected to the input terminals of the delay line 17 and the Ex-Nor gate 18, and the output terminal of the delay line 17 is connected to the Ex-Nor gate 18.
It is connected to the other input terminal of the Nor gate 18. The output terminal of Ex-Nor gate 18 is connected to the other input terminal of And gates 14 and 16, and these output terminals are connected to the S terminal and R terminal of SR flip-flop 19, respectively. The Q terminal output of the SR flip-flop 19 is supplied to the input of the Ex-Or gate 15, the output of which is connected to the clock output 9. On the other hand, the terminal output of flip-flop 19 is supplied to data output terminal 11.

FIG. 4 shows a time chart of signal waveforms at various parts in FIG. 3. d is signal input terminal 1
e is the output signal of the inverter 13, f is the output signal of the delay line 17 whose delay time is 1/2 of the clock cycle, g is the output signal of the Ex-Nor gate 18, h and i are the And gate 14, respectively. , 16 output signals, j, k are each SR flip-flop 19
Q terminal, the output signal of the terminal, l is the output signal of the Ex-Or gate 15.

In the PM code, in order to synchronize the bit phase, it is necessary to fix the first bit of data to either logic "0" or "1", or to use a synchronization pull-in pattern as described in the conventional example. The first bit "1" of the input signal d in FIG. 4 is a dummy bit added to the beginning of the data.

Next, the operation in this embodiment will be explained. As shown in the input signal d, in the PM code, the data changes from “1” to “0” or from “0” to “1”.
When the pulse width changes to , the pulse width becomes twice as long as when the pulse width changes to "1" or "0" continuously. Focusing on this, the output signal e of the inverter 13 and the delay line 17 are used to convert this signal e to ₂ of the clock period T0.
By inputting the signal f delayed by 1/2 to the Ex-Nor gate 18, the data change point can be detected, and the signal g whose logic level becomes "1" when the data changes is detected by the Ex-Nor gate 18. It is obtained at the output of the Nor gate 18. Therefore, the inverter 13, delay circuit 17, and Ex-Nor gate 18 constitute a change point detection circuit 21.

Next, this signal g is separated into a signal corresponding to a change in data from "1" to "0" and a signal corresponding to a change in data from "0" to "1". That is, the signal g and the input signal d are connected to the AND gate 14.
A signal h whose logic level becomes "1" when the data changes from "1" to "0" is obtained at its output terminal. On the other hand, the signal g and the inverter output signal e are input to the AND gate 16, and a signal i which becomes "1" when the data changes from "0" to "1" is obtained at its output terminal. These signals h and i are sent to the S terminal of the SR flip-flop 19, respectively.
By inputting to the R terminal, data k is input to the terminal.
is obtained. That is, the AND gates 14 and 16 and the flip-flop 19 constitute a data reproducing circuit 22. Also, Q terminal output signal j and input signal d
is input to the Ex-Or gate 15, and the clock l is obtained at its output terminal. Therefore, the Ex-Or gate 15 constitutes a clock recovery circuit 23.

In the above embodiment, as shown in the time chart of FIG. 4, regardless of whether the last bit is "1" or "0", due to the presence of the delay line 17, the R of the SR flip-flop 19 is output immediately after the last data. Since the signal i input to the terminal becomes "1", the above
The SR flip-flop 19 is always reset after data is completed. Therefore, by using this reproducing device, it is possible to repeatedly reproduce data and clocks of any number of bits by simply adding one dummy bit of "1" to the beginning of the data on the transmitting side.

As explained above, if the reproduction device according to the present invention is used, only one dummy bit needs to be added to the beginning of data for signal reproduction in a partially synchronous transmission method using PM codes, and it is possible to use a logic gate. Since data and clocks can be easily reproduced in combination with a delay line, the processing time can be improved, and the cost can be reduced by simplifying the circuit.

[Brief explanation of the drawing]

Fig. 1 is a logic circuit diagram showing a conventional playback device in a transmission system using PM codes, Fig. 2 is a time chart showing signal waveforms of the main parts in Fig. 1,
FIG. 3 is a logic circuit diagram showing an embodiment of the PM code reproducing apparatus according to the present invention, and FIG. 4 is a time chart showing signal waveforms at various parts in FIG. 1: Signal input terminal, 2: One shot circuit, 3:
Data discrimination circuit, 4: Phase comparator, 5: Low-pass filter, 6: Voltage controlled oscillator, 7: Frequency dividing circuit, 9:
Clock output terminal, 11: Data output terminal, 12:
PLL circuit, 17: delay line, 21: change point detection circuit, 22: data regeneration circuit, 23: clock regeneration circuit.

Claims (1)

[Claims] 1. One dummy bit is added at the beginning.
In a device that receives a PM code signal, an exclusive NOR gate is used to detect a data change point from the received signal and a signal delayed by half of the clock period, and the data change point is A change from logic "0" to "1" is handled by a change point detection circuit that generates a signal, and a gate circuit that ANDs the signal corresponding to the change point with the above received signal and its inverted signal. and a signal corresponding to a change from logic "1" to "0", and sets and resets a flip-flop circuit using these separated signals to reproduce data; 1. A PM code reproducing device comprising: a clock reproducing circuit that regenerates a clock from reproduced data and the received signal using an exclusive OR gate.