JPS5613859A - Pm code reproducing device - Google Patents
Pm code reproducing deviceInfo
- Publication number
- JPS5613859A JPS5613859A JP8971879A JP8971879A JPS5613859A JP S5613859 A JPS5613859 A JP S5613859A JP 8971879 A JP8971879 A JP 8971879A JP 8971879 A JP8971879 A JP 8971879A JP S5613859 A JPS5613859 A JP S5613859A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- data
- circuit
- logic
- turns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
Abstract
PURPOSE:To shorten the processing time as well as simplify the circuit constitution, by reproducing the clock and the data from the received signal underwent the waveform shaping and by the combination of the logic gate and the delay line. CONSTITUTION:Input signal d of the PM code received the waveform shaping is supplied to changing point detecting circuit 21 consisting of inverter 13, delaying circuit 17 and Ex-Nor gate 18. And when the data given from circuit 21 changes, signal g which turns to logic 1 is obtained. When the data changed to 0 from 1 via data reproducing circuit 22 comprising AND gates 14 and 16 plus FF19 and by signal d, output signal e of inverter 13 and signal g each, signal h which turns to logic 1 is obtained along with signal i which turns to logic 1 when the data changes to 1 from 0. With these two signals, data k is obtained at terminal Q' of FF19. At the same time, Q terminal output signal j of FF19 and signal d are supplied to Ex-OR gate 23, and then clock l is obtained at output terminal 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8971879A JPS5613859A (en) | 1979-07-13 | 1979-07-13 | Pm code reproducing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8971879A JPS5613859A (en) | 1979-07-13 | 1979-07-13 | Pm code reproducing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5613859A true JPS5613859A (en) | 1981-02-10 |
JPS6316935B2 JPS6316935B2 (en) | 1988-04-12 |
Family
ID=13978540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8971879A Granted JPS5613859A (en) | 1979-07-13 | 1979-07-13 | Pm code reproducing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5613859A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59171244A (en) * | 1982-08-19 | 1984-09-27 | インタ−ナシヨナル・スタンダ−ド・エレクトリツク・コ−ポレイシヨン | 2-phase decoder |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5081463A (en) * | 1973-11-20 | 1975-07-02 |
-
1979
- 1979-07-13 JP JP8971879A patent/JPS5613859A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5081463A (en) * | 1973-11-20 | 1975-07-02 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59171244A (en) * | 1982-08-19 | 1984-09-27 | インタ−ナシヨナル・スタンダ−ド・エレクトリツク・コ−ポレイシヨン | 2-phase decoder |
Also Published As
Publication number | Publication date |
---|---|
JPS6316935B2 (en) | 1988-04-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6467029A (en) | Phase matching circuit | |
CA2201695A1 (en) | Phase detector for high speed clock recovery from random binary signals | |
ES8507743A1 (en) | Debounce circuit providing synchronously clocked digital signals. | |
GB1265530A (en) | ||
JPS5613859A (en) | Pm code reproducing device | |
JPS555544A (en) | Timing pulse generation circuit | |
JPS5592040A (en) | Ttl gate circuit | |
JPS57210718A (en) | Signal change detecting circuit | |
JPS5710566A (en) | Decoding circuit | |
JPS5334428A (en) | Detecting circuit for video information | |
JPS5244125A (en) | Variable length interface circuit | |
JPS54147765A (en) | Frequency division circuit | |
FR2433263A1 (en) | Control circuit for flip=flop - has inverter with two NOR circuits, OR circuits and flip=flop using time signal (BE 8.2.80) | |
JPS57194378A (en) | Test circuit of electronic clock | |
JPS5761328A (en) | Detection circuit of coincidence of changing point of two kinds of clock signal | |
JPS5394857A (en) | Oscillation frequency converter circuit | |
JPS56122520A (en) | Phase difference detecting circuit | |
JPS5769433A (en) | Clock signal controlling system | |
JPS5523613A (en) | Reproducing system of timing information | |
JPS5712479A (en) | Address inverting circuit | |
JPS56147236A (en) | Adding circuit | |
JPS6413808A (en) | Latching circuit | |
JPS5793745A (en) | Transmission system for all mark | |
JPS57210412A (en) | Muting system of pcm recording and reproducing apparatus | |
JPS5571324A (en) | Gate circuit |