JPS5793745A - Transmission system for all mark - Google Patents
Transmission system for all markInfo
- Publication number
- JPS5793745A JPS5793745A JP17020880A JP17020880A JPS5793745A JP S5793745 A JPS5793745 A JP S5793745A JP 17020880 A JP17020880 A JP 17020880A JP 17020880 A JP17020880 A JP 17020880A JP S5793745 A JPS5793745 A JP S5793745A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- mark
- frequency
- ternary value
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Sheets, Magazines, And Separation Thereof (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To enable the transmission of all mark signal required for the test for margin of sinusoidal wave superimposition, by applying a signal frequency-dividing a clock signal into two to the input of a unipolar-ternary value conversion circuit. CONSTITUTION:In performing a sinusoidal wave superimposing margin test, a switch SW is opened and an input 641 of an NAND gate 64 is at high level, then the output of NAND gate 67, 68 is always at high level. On the other hand, a clock signal synchronized with a ternary value signal is frequency-divided into two at a dioding circuit constituted with a D-FF63 to produce a noninverting frequency division signal DN and an inverting frequency division signal DI and they are applied to a unipolar-ternary value conversion circuit 62 via NAND gates 65, 66, 69, 70. Thus, to +, - signal inputs 621, 622 of the circuit 62, alternately (0, 1) and (1, 0) are inputted as (DN, DI)=(0, 1), (1, 0)... to output an all mark signal OT.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17020880A JPS5793745A (en) | 1980-12-04 | 1980-12-04 | Transmission system for all mark |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17020880A JPS5793745A (en) | 1980-12-04 | 1980-12-04 | Transmission system for all mark |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5793745A true JPS5793745A (en) | 1982-06-10 |
JPS6335144B2 JPS6335144B2 (en) | 1988-07-13 |
Family
ID=15900663
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17020880A Granted JPS5793745A (en) | 1980-12-04 | 1980-12-04 | Transmission system for all mark |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5793745A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0215748A (en) * | 1988-07-04 | 1990-01-19 | Nec Corp | System for evaluating digital transmission device |
-
1980
- 1980-12-04 JP JP17020880A patent/JPS5793745A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0215748A (en) * | 1988-07-04 | 1990-01-19 | Nec Corp | System for evaluating digital transmission device |
Also Published As
Publication number | Publication date |
---|---|
JPS6335144B2 (en) | 1988-07-13 |
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