JPS56149827A - 90 phase difference signal generating circuit - Google Patents

90 phase difference signal generating circuit

Info

Publication number
JPS56149827A
JPS56149827A JP5378780A JP5378780A JPS56149827A JP S56149827 A JPS56149827 A JP S56149827A JP 5378780 A JP5378780 A JP 5378780A JP 5378780 A JP5378780 A JP 5378780A JP S56149827 A JPS56149827 A JP S56149827A
Authority
JP
Japan
Prior art keywords
signal
output signal
phase difference
signals
signal generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5378780A
Other languages
Japanese (ja)
Inventor
Kazuo Sato
Tsuguo Otsuki
Mikio Murozaki
Yoshio Takekoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5378780A priority Critical patent/JPS56149827A/en
Publication of JPS56149827A publication Critical patent/JPS56149827A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)

Abstract

PURPOSE:To generate two signals of which duty ratio is 1 to 7, without being accompanied with an unnecessary wave, and also exactly having the 90 deg. phase difference, even in the event of time lag of a logical operation signal in the logical circuit including the flip-flop FF. CONSTITUTION:A repeat pulse signal (a) is provided to the inverter 5, and an output signal (b) is obtained. On the other hand, the signal (a) is provided to the terminal C of the FF 1, is frequency-divided into two, and a Q output signal (c) and a Q' output signal (d) are obtained. The signal (c) is provided to the terminal C of the FF2, is frequency-divided into two, and a Q' output signal (e) is generated. The AND gate 3 generates an output signal (f) under the condition of coincidence of the signal (b), the signal (d) and the signal (e). The AND gate 4 generates an output signal (g) under the condition of coincidence of the signal (b) the signal (c) and the signal (e). The signal (f) and the signal (g) are signals whose duty ratio is 1 to 7, respectively, and whose mutual phase difference becomes 90 deg., and these signals are used for the carrier wave of a modulator.
JP5378780A 1980-04-23 1980-04-23 90 phase difference signal generating circuit Pending JPS56149827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5378780A JPS56149827A (en) 1980-04-23 1980-04-23 90 phase difference signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5378780A JPS56149827A (en) 1980-04-23 1980-04-23 90 phase difference signal generating circuit

Publications (1)

Publication Number Publication Date
JPS56149827A true JPS56149827A (en) 1981-11-19

Family

ID=12952521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5378780A Pending JPS56149827A (en) 1980-04-23 1980-04-23 90 phase difference signal generating circuit

Country Status (1)

Country Link
JP (1) JPS56149827A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6359430U (en) * 1986-10-02 1988-04-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6359430U (en) * 1986-10-02 1988-04-20

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