JPS5669929A - Pulse-width modulating circuit - Google Patents

Pulse-width modulating circuit

Info

Publication number
JPS5669929A
JPS5669929A JP14676279A JP14676279A JPS5669929A JP S5669929 A JPS5669929 A JP S5669929A JP 14676279 A JP14676279 A JP 14676279A JP 14676279 A JP14676279 A JP 14676279A JP S5669929 A JPS5669929 A JP S5669929A
Authority
JP
Japan
Prior art keywords
pulse
outputs
counter
latches
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14676279A
Other languages
Japanese (ja)
Other versions
JPS6059776B2 (en
Inventor
Tsuneo Imai
Meiki Yahata
Hideo Suzuki
Shunsuke Yoda
Tadamichi Kawasaki
Toshiro Nose
Takahiko Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Toshiba Corp
Nippon Telegraph and Telephone Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Nippon Telegraph and Telephone Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14676279A priority Critical patent/JPS6059776B2/en
Publication of JPS5669929A publication Critical patent/JPS5669929A/en
Publication of JPS6059776B2 publication Critical patent/JPS6059776B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/82—Digital/analogue converters with intermediate conversion to time interval

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To obtain the pulse-width-modulated signal of digital data, by generating a pulse that rises when bits of the data all disagree with those of a counter counting continuously and falls when all bits agree. CONSTITUTION:Input signal 6 is operated as prescribed by arithmetic part 5 under the control of outputs 4a-4f of counter 3 and when the contents of counter 3 are all ''0'', they are inputted to latches 8a-8e. When outputs 4a-4f of counter 3 all disagree with outputs 9a-9e of latches 8a-8e and 3f is at ''1'', output 16 is at ''0'', setting flip-flop 20. On the other hand, when both outputs agree completely and 3f is at ''0'', output 15 is at ''0'', resetting flip-flop 20. Output 23 varies in pulse width the contents of latches 8a-8e.
JP14676279A 1979-11-13 1979-11-13 pulse width modulation circuit Expired JPS6059776B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14676279A JPS6059776B2 (en) 1979-11-13 1979-11-13 pulse width modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14676279A JPS6059776B2 (en) 1979-11-13 1979-11-13 pulse width modulation circuit

Publications (2)

Publication Number Publication Date
JPS5669929A true JPS5669929A (en) 1981-06-11
JPS6059776B2 JPS6059776B2 (en) 1985-12-26

Family

ID=15414985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14676279A Expired JPS6059776B2 (en) 1979-11-13 1979-11-13 pulse width modulation circuit

Country Status (1)

Country Link
JP (1) JPS6059776B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03147426A (en) * 1989-11-01 1991-06-24 Sharp Corp Data pulse width conversion circuit
JP2006020109A (en) * 2004-07-02 2006-01-19 Nec Electronics Corp Pulse width modulator circuit
US7394319B2 (en) 2005-05-10 2008-07-01 Nec Electronics Corporation Pulse width modulation circuit and multiphase clock generation circuit
CN101841329A (en) * 2010-06-12 2010-09-22 中兴通讯股份有限公司 Phase-locked loop, and voltage-controlled device and method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03147426A (en) * 1989-11-01 1991-06-24 Sharp Corp Data pulse width conversion circuit
JP2006020109A (en) * 2004-07-02 2006-01-19 Nec Electronics Corp Pulse width modulator circuit
US7554373B2 (en) 2004-07-02 2009-06-30 Nec Electronics Corporation Pulse width modulation circuit with multiphase clock
JP4563737B2 (en) * 2004-07-02 2010-10-13 ルネサスエレクトロニクス株式会社 Pulse width modulation circuit
US7394319B2 (en) 2005-05-10 2008-07-01 Nec Electronics Corporation Pulse width modulation circuit and multiphase clock generation circuit
CN101841329A (en) * 2010-06-12 2010-09-22 中兴通讯股份有限公司 Phase-locked loop, and voltage-controlled device and method

Also Published As

Publication number Publication date
JPS6059776B2 (en) 1985-12-26

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