JPS57204631A - Modulating circuit of pulse width - Google Patents

Modulating circuit of pulse width

Info

Publication number
JPS57204631A
JPS57204631A JP9067481A JP9067481A JPS57204631A JP S57204631 A JPS57204631 A JP S57204631A JP 9067481 A JP9067481 A JP 9067481A JP 9067481 A JP9067481 A JP 9067481A JP S57204631 A JPS57204631 A JP S57204631A
Authority
JP
Japan
Prior art keywords
output
circuit
counter
bit
pulse width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9067481A
Other languages
Japanese (ja)
Inventor
Yutaka Oota
Masaru Hashirano
Tatsuo Wada
Seiji Yamaguchi
Toshiomi Yabu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9067481A priority Critical patent/JPS57204631A/en
Publication of JPS57204631A publication Critical patent/JPS57204631A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

Abstract

PURPOSE:To avoid a malfunction caused by dissidence, by setting a storage circuit with the highest bit output of a counter that produces a comparing output and at the same time latching the digital error signal. CONSTITUTION:A flip-flop FF6 is set by the output C of an n-bit binary counter 5 that counts clock pulses CK2, and at the same time the output of an n-bit latch circuit 3 is latched to an n-bit latch circuit 7. When coincidence is obtained between the contents of the counter 5 and that of the circuit 7, an output is delivered from a coincidence circuit 4 to reset the FF6. Thus the output of the circuit 4 is obtained without fail although the output of the circuit 3, i.e., a digital error signal has a change during a comparing action.
JP9067481A 1981-06-11 1981-06-11 Modulating circuit of pulse width Pending JPS57204631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9067481A JPS57204631A (en) 1981-06-11 1981-06-11 Modulating circuit of pulse width

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9067481A JPS57204631A (en) 1981-06-11 1981-06-11 Modulating circuit of pulse width

Publications (1)

Publication Number Publication Date
JPS57204631A true JPS57204631A (en) 1982-12-15

Family

ID=14005081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9067481A Pending JPS57204631A (en) 1981-06-11 1981-06-11 Modulating circuit of pulse width

Country Status (1)

Country Link
JP (1) JPS57204631A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63160411A (en) * 1986-12-24 1988-07-04 Toshiba Corp Pulse width modulation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63160411A (en) * 1986-12-24 1988-07-04 Toshiba Corp Pulse width modulation circuit

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