JPS57160214A - Flip-flop circuit and counter circuit using it - Google Patents

Flip-flop circuit and counter circuit using it

Info

Publication number
JPS57160214A
JPS57160214A JP56045552A JP4555281A JPS57160214A JP S57160214 A JPS57160214 A JP S57160214A JP 56045552 A JP56045552 A JP 56045552A JP 4555281 A JP4555281 A JP 4555281A JP S57160214 A JPS57160214 A JP S57160214A
Authority
JP
Japan
Prior art keywords
circuit
synchronizing
signal
phi
receives
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56045552A
Other languages
Japanese (ja)
Inventor
Takashi Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56045552A priority Critical patent/JPS57160214A/en
Publication of JPS57160214A publication Critical patent/JPS57160214A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To prevent malfunction due to racing by providing a singal delay means to a positive feedback loop which constitutes an FF circuit. CONSTITUTION:An FF circuit consists of an inverter circuit IN1 which receives a write signal in synchronizing with clock pulses phi, an inverter circuit IN2 which receives the output signal of the circuit IN1, an inverter circuit IN3 which receives the output signal of the circuit IN2 synchronizing with the inverted signal phi' of the pulses phi and then supplies its output signal to the input terminal of the circuit IN2, and a delay circuit D inserted between the circuits IN2 and IN3. In this FF circuit, when the wirting of the signal in performed synchronizing with the pulses phi and holding operation synchronizing with the pulses phi' are changed over to each other, the undefined logical level transition time T1 of the circuits IN1 and IN3 is made shorter than the signal transmission delay time T2' of a positive feedback loop by the circuit. Therefore, malfunction due to racing is prevented.
JP56045552A 1981-03-30 1981-03-30 Flip-flop circuit and counter circuit using it Pending JPS57160214A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56045552A JPS57160214A (en) 1981-03-30 1981-03-30 Flip-flop circuit and counter circuit using it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56045552A JPS57160214A (en) 1981-03-30 1981-03-30 Flip-flop circuit and counter circuit using it

Publications (1)

Publication Number Publication Date
JPS57160214A true JPS57160214A (en) 1982-10-02

Family

ID=12722519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56045552A Pending JPS57160214A (en) 1981-03-30 1981-03-30 Flip-flop circuit and counter circuit using it

Country Status (1)

Country Link
JP (1) JPS57160214A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6359212A (en) * 1986-08-29 1988-03-15 Toshiba Corp Latch circuit
JPS63238712A (en) * 1987-03-26 1988-10-04 Mitsubishi Electric Corp Flip-flop circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6359212A (en) * 1986-08-29 1988-03-15 Toshiba Corp Latch circuit
JPS63238712A (en) * 1987-03-26 1988-10-04 Mitsubishi Electric Corp Flip-flop circuit

Similar Documents

Publication Publication Date Title
AU6392686A (en) Digital intergrated circuit
KR900014970A (en) Synchronous circuit
IT1236578B (en) Type D flip=flop to type B flip=flop converter circuit
EP0243235A3 (en) Noise pulse suppressing circuit in a digital system
US4933571A (en) Synchronizing flip-flop circuit configuration
TW257906B (en) ECL differential multiplexing circuit
JPS57160214A (en) Flip-flop circuit and counter circuit using it
ATE28770T1 (en) SIMPLE TIMED LOCKING CIRCUIT.
GB1495838A (en) Synchronous shift register
MX156122A (en) IMPROVEMENTS IN REGENERATION CIRCUIT OF PERIODIC INSTANTS
EP0306234A3 (en) A flip-flop arrangement
JPS56117423A (en) Binary coding circuit by multistage threshold level
JPS6465944A (en) Multiframe synchronization circuit
JPS6437114A (en) D flip flop circuit with set/reset function
AU583921B2 (en) Circuit arrangements for recovering the clock rate of an isochronous binary signal
JPS5768929A (en) Flip-flop circuit
JPS6436218A (en) Frequency division circuit
FR2433263A1 (en) Control circuit for flip=flop - has inverter with two NOR circuits, OR circuits and flip=flop using time signal (BE 8.2.80)
JPS55147821A (en) Digital filter
JPS5689145A (en) Asynchronous type data transmission device
JPS55137751A (en) Transmission data reproducing circuit
JPS56161748A (en) Data reception circuit
JPS5761338A (en) Counter circuit
FR2246123A1 (en) Logical selective electronic filter - gives first logic output function when its input receives precise frequency
JPS5511624A (en) Holding device of multiple selection signal