JPS6436218A - Frequency division circuit - Google Patents

Abstract

PURPOSE:To make the duty nearly 50% by providing an n-stage of D type FF, a logic circuit, and a D type FF circuit using an output of the logic circuit as the clock input, using the inverted output as the data input and using the output signal for plural D type FF input data. CONSTITUTION:The output signal S10 of the D type FF5 goes to H at time t1 when the clock signal S2 rises at first from a time t0 when a reset signal S1 goes to H. Since the D type FF3 uses the clock signal inverted by the inverter 7 to latch the signal S10 at a time t2, the signal S6 goes to H. The said D type FF5 inverts the output synchronously with the time t3 when the clock signal S2 descends next and the output signal S10 goes to L. Since the D type FF3 latches the signal S10 at a time t4, the signal S6 goes to L. In checking the output signal S10 of the D type FF5, the duty is brought into 50%.