JPS5779727A - Flip-flop circuit - Google Patents

Flip-flop circuit

Info

Publication number
JPS5779727A
JPS5779727A JP55156217A JP15621780A JPS5779727A JP S5779727 A JPS5779727 A JP S5779727A JP 55156217 A JP55156217 A JP 55156217A JP 15621780 A JP15621780 A JP 15621780A JP S5779727 A JPS5779727 A JP S5779727A
Authority
JP
Japan
Prior art keywords
tri
state inverter
flop circuit
flip
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55156217A
Other languages
Japanese (ja)
Inventor
Setsuzo Tachibana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55156217A priority Critical patent/JPS5779727A/en
Publication of JPS5779727A publication Critical patent/JPS5779727A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type

Abstract

PURPOSE:To increase the degree of integration through addition of preset function with less number of elements, by constituting a gate consisting of inverters of master latch and slave latch with a tri-state inverter. CONSTITUTION:A tri-state inverter 11 is used for a master latch 1 constituting a master slave flip-flop circuit and a gate of a slave latch 2. The tri-state inverter 11 turns off at load timing and the tri-state inverter 13 turns on, allowing to ?make independent of the phase of clock.
JP55156217A 1980-11-06 1980-11-06 Flip-flop circuit Pending JPS5779727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55156217A JPS5779727A (en) 1980-11-06 1980-11-06 Flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55156217A JPS5779727A (en) 1980-11-06 1980-11-06 Flip-flop circuit

Publications (1)

Publication Number Publication Date
JPS5779727A true JPS5779727A (en) 1982-05-19

Family

ID=15622911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55156217A Pending JPS5779727A (en) 1980-11-06 1980-11-06 Flip-flop circuit

Country Status (1)

Country Link
JP (1) JPS5779727A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0440113A (en) * 1990-06-06 1992-02-10 Fujitsu Ltd Flip-flop circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0440113A (en) * 1990-06-06 1992-02-10 Fujitsu Ltd Flip-flop circuit

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