JPS54148463A - Jk flip-flop - Google Patents

Jk flip-flop

Info

Publication number
JPS54148463A
JPS54148463A JP5779578A JP5779578A JPS54148463A JP S54148463 A JPS54148463 A JP S54148463A JP 5779578 A JP5779578 A JP 5779578A JP 5779578 A JP5779578 A JP 5779578A JP S54148463 A JPS54148463 A JP S54148463A
Authority
JP
Japan
Prior art keywords
output
master
change
input
following
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5779578A
Other languages
Japanese (ja)
Inventor
Yasuo Ueji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5779578A priority Critical patent/JPS54148463A/en
Publication of JPS54148463A publication Critical patent/JPS54148463A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits

Abstract

PURPOSE:To eliminate the limitation for use of JKFF and thus to increase the flexibility of designing by providing the means which varies the state of the master FF following the change of the JK input. CONSTITUTION:The logic circuit is provided at the input part of master FF so that output X and Y of master FF vary following the change of input J and K during the active level period of the clock. Thus, output S and R of OR gate O1 and O2 are actuated by the logic formula expressed by Eq. 1. Here, output X and Y of master FF vary following the change of J and K each, and thus the output of slave FF operates as shown in the display of the truth value. Thus, output X and Y follow the change of J and K, and thus the using limitaion can be eliminated for JKFF. As a result, the flexibility of designing can be increased.
JP5779578A 1978-05-15 1978-05-15 Jk flip-flop Pending JPS54148463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5779578A JPS54148463A (en) 1978-05-15 1978-05-15 Jk flip-flop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5779578A JPS54148463A (en) 1978-05-15 1978-05-15 Jk flip-flop

Publications (1)

Publication Number Publication Date
JPS54148463A true JPS54148463A (en) 1979-11-20

Family

ID=13065817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5779578A Pending JPS54148463A (en) 1978-05-15 1978-05-15 Jk flip-flop

Country Status (1)

Country Link
JP (1) JPS54148463A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59190712A (en) * 1983-04-13 1984-10-29 Agency Of Ind Science & Technol Josephson logical circuit
JPS6457815A (en) * 1988-05-31 1989-03-06 Toshiba Corp Flip-flop circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5328998A (en) * 1976-08-30 1978-03-17 Hitachi Koki Co Ltd Automatic return apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5328998A (en) * 1976-08-30 1978-03-17 Hitachi Koki Co Ltd Automatic return apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59190712A (en) * 1983-04-13 1984-10-29 Agency Of Ind Science & Technol Josephson logical circuit
JPH0220015B2 (en) * 1983-04-13 1990-05-07 Kogyo Gijutsuin
JPS6457815A (en) * 1988-05-31 1989-03-06 Toshiba Corp Flip-flop circuit
JPH0453450B2 (en) * 1988-05-31 1992-08-26 Tokyo Shibaura Electric Co

Similar Documents

Publication Publication Date Title
JPS54148463A (en) Jk flip-flop
JPS54154964A (en) Programable counter
JPS54121652A (en) Jk flip-flop circuit
JPS5647826A (en) Waveform generator
JPS5510688A (en) Control circuit
JPS5469936A (en) Level converter circuit
JPS53142844A (en) Information processor
JPS52132632A (en) Input/output control circuit
USD180581S (en) Wall panel
JPS5539474A (en) Flip-flop circuit
JPS5779727A (en) Flip-flop circuit
JPS551735A (en) Synchronism detection circuit
SU141646A1 (en) Matrix model of a system of linear algebraic equations
JPS52142469A (en) Semiconductor circuit
JPS53108290A (en) Static induction transistor logic
JPS5672533A (en) Latch circuit
JPS5329062A (en) Control circuit of counter
JPS5379339A (en) Basic circuit of progammable cmos logical array
JPS53117183A (en) Sequential control circuit
JPS5257752A (en) Average value arithmetic circuit
JPS55166330A (en) Integrated circuit device
JPS54140446A (en) Pulse generator
JPS53121532A (en) 1-bit delay type full adder
JPS5373951A (en) Flip-flop circuit
JPS5613849A (en) Data transmitting device

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080419

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090419

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees