JPS59190712A - Josephson logical circuit - Google Patents

Abstract

PURPOSE:To obtain a J-KFF circuit which operates only by a DC power source and consists of only current transfer circuits without including any resistance element by providing two self-setting AND gates and two current transfer circuits. CONSTITUTION:A self-setting AND gate SR1 ANDs an input signal to an input terminal K with the output OOUT of a slave FF current transfer circuit S, and a self-setting AND gate SR2 ANDs an input terminal to an input terminal J with the output of a master FF current transfer circuit M. The circuit M is driven by an external clock signal C and the circuit S is driven by the inverted signal -C of the clock signal C. Then, the circuit M is controlled by output signals of the self-setting AND gates SR1 and SR2 and the circuit S is placed in the state depending upon the state of the circuit M.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a digital logic circuit, and more particularly to a J-flip 70 logic circuit constructed using digital logic elements.

(2) Background of the Technology With the development of information processing technology, information processing devices such as electronic computers are becoming faster and larger in capacity.

Attempts have been made to apply a so-called diH-Sefson element that utilizes superconductivity as one of the functional elements constituting such an information processing device.

Such an element has the advantage of being able to operate at a higher speed than an element using a conductive material such as silicon or gallium or arsenic.

B Button: Prior Art and Problems A J-7 lipfrog circuit, which is one of the logic circuits constructed using the above-mentioned J-7 circuit elements as functional elements, has a conventional configuration as shown in FIG. ing.

In the figure, J1 to J. R7
~RI! is resistance and L is inductance 0 or Va
cl~'Vac4 is an alternating current bias current source, and DC is a direct current source.

For example, when the critical N current of the second element J4 is suppressed when the flip-flop circuit i is connected to such J-, that is, the second fourth element J4.

When a signal current is applied to the input terminal JINi while the signal current Qout is being outputted (inactive state), the Jirocefson element J is brought into an inactive state.

Therefore, the current from the bias current source Vacl passes through resistors R, , R, and further passes through resistor R2 to the reference 1st position (
flows to ground potential). As a result, the digital display element J is rendered inactive. Since the current sensor element JI+ is inactive, the current from the direct current source DC flows through the current sensor element J6. For this reason,
The dielectric element J8 is rendered inactive, and therefore the dielectric element J9 is rendered superconducting.

On the other hand, since the girosefson element J is inactive,
Ji■Se7nn element J'? The critical current is suppressed iTl,n
No state M (active state M), therefore diW cefnon element J 1
o is assumed to be inactive.

Therefore, the current from the bias current source Vac4 flows through the resistor 1
2, the input element J4 is converted to an inactive state. The current from the bias current source Vae3 is
It passes through the Josephson element J and reaches the reference potential.

As a result, an output is taken out from the output terminal Jout (Q).

The machine to which the signal current 1 is applied to the input terminal KINi performs the same operation as above, and the output terminal Kout(Q)
Output is taken from.

Like this: In the eJ-flip-flop circuit,
Since the positive circuit is constructed by combining a latching gate and a flip-flop, the latching gate cannot be reset unless a bias current is applied in the form of a current. Therefore, two types of current, a DC power source and an AC R'Wl source, are required.

Since it contains t, #, and anti-Rr-R+t, the manufacturing process is complicated, and the manufacturing yield and reliability are reduced.

(42 Object of the Invention The present invention eliminates the problems with the conventional J-type flip-flop circuit, can operate with only a DC power supply, and is composed only of a current transfer circuit without a resistive element. This provides a flip-flop circuit for J-.

(6) Structure of the Invention Therefore, according to the present invention, the first and second self-resetting AND gates, a master flip-flop current transfer circuit, and a slave flip-flop current transfer circuit are provided. Self-resetting AND
The gate takes as input signals the signal passing through the transistor gate in the second branch of the slave flip-flop current transfer circuit and the first external input signal, and outputs the AND output signal from the master flip-flop current transfer circuit. the second self-resetting AND gate is the input signal to the input signal of the Sefson device gate in the first branch of the slave flip-flop current transfer circuit; The Sefson element gate takes the signal passing through the cell 7 resetting AND gate and the second external input signal as input signals, and uses the logical product output as the master flip 70. Josephson device gates serving as an input signal and a signal appearing in each branch as an input signal of the slave flip-flop current transfer circuit; Provided is a Josephson logic circuit which uses an output signal of the master flip-flop current transfer circuit and a complementary signal of the clock signal as input signals, respectively, and uses an AND output as an output signal.

Hereinafter, the present invention will be explained in detail with reference to examples.

(7) Embodiment of the Invention FIG. 2 shows a J'-K flip 70 tube circuit according to the present invention.

In the same figure, Jlol to Jlall are Josephson elements, R8+, S R1 are cell 7 resetting AND
Gate, M is master 7 flip-flop current transfer circuit, S is sleeve, flip-flop current transfer circuit, Va
-Vc is a bias current source.

Here, the seven reset AND gates SR+M are driven by an external clock signal C, and the slave flip-flop current transfer circuit S is driven by an inverted signal σ of the clock signal C.

The master 7 flip-flop current transfer circuit M includes a self-resetting AND group 1-8RI,
Controlled by the output signal of SR1, and slave
The state of the flip-flop current transfer circuit S is set depending on the state of the master flip-flop current transfer circuit M.

That is, for example, the output Qout is )-I (HIgh)"
When the input signal pulse J is applied to the input terminal JIN in synchronization with the clock signal C1 when the level Qout is low, the DC offset current D
Josephson element J, rendered inactive by C.

4 (Thus, the bias current flowing through the Josephson element J, . The voltage flows through the sensor element JI.3, flows into the slave flip-flop voltage transfer circuit S, and flows to the reference potential (ground potential).

Then, when an input signal pulse K is applied to the input terminal KIN in synchronization with the clock signal C, a DC offset current D
Josephson element 10 rendered inactive by el
1i, the bias current flowing through the Josephson element 102 is reduced to the input signal pulse K and the slave signal.
Since the Josephson element J1° is rendered inactive by the output Qout of the flip-flop current transfer circuit S, a current flows through the Josephson element J1°.

The Josephson element J1°11 flows 1! The current and clock signal CI thus flow to the current potential of the other branch in the master 7 flip-flop current transfer circuit M1.

The master 7 lip-flop current transfer circuit Mp output Q
m and the inverted signal C of the clock C, the Josephson element J 1 o g is made inactive, and the bias current Ia
flows through the Josephson element JIoy, and the output of the slave slip-flop current transfer circuit S becomes Qout.

In addition, when simultaneous input signal pulses are applied to the input terminals KrN and JTNl, the outputs QQout and Qonti of the slave-7 lip-flop current transfer circuit S will be used to select either the self-resetting AND gate SR1 or SR. One is output and inverts the master and slave 7 flip-flop current transfer circuits MSS, respectively.

When the J-7 lip-flop circuit according to the present invention shown in FIG. 2 is represented by logic symbols, it is represented as shown in FIG. 3.

Further, the operation of the J-Flip flop circuit according to the present invention is shown in a timing chart as shown in FIG.

In the embodiment of the J- flip-flop circuit according to the present invention, it has been disclosed that there are difficulties when applying the clock signal C9 from the outside, but the present invention is not limited to this. For example, by providing the self-resetting inverter circuit shown in FIG. It can be generated inside the precision circuit. In the same figure, JB
. .

J. 2 indicates a Josephson element, and Cout indicates a clock signal applied from the outside.

(8) Effects of the Invention According to the present invention as described above, a 7-rip 70-g circuit is connected to J- using a Josephson element, and only a current transfer circuit is connected to the t
This can be configured as follows. Therefore, there is no need to use a resistor as in the prior art, the number of Josephson elements can be reduced, and furthermore, since it is not necessary to use an AC bias power supply, a flip-flop circuit is included in the J-. It is possible to improve the degree of integration and manufacturing yield of the J4 Cefson integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram showing the configuration of a conventional J-type flip-flop circuit, and FIG. 2 is a wiring diagram showing the configuration of a J-type flip-flop circuit according to the present invention. FIG. 3 is a block diagram showing the logical configuration of the J-71J block 70 shown in FIG. 2, and FIG. 3 is a timing chart showing the operating state of the J-K flip-flop circuit. Furthermore, FIG. 5-' is a wiring diagram showing an example of a clock signal → generation circuit that is applied to generate all the internal polarization and p-deviation signals in the integrated circuit device. In the figure, J, ~ J1゜+J1o1~J1゜8 and J
,. 1. J. ! is a Josephson element, R1 to R□ are resistances, and L is an inductance. Further, SR is a self-resetting AND gate, M is a master flip-flop current transfer circuit, and S is a slave flip-flop current transfer circuit. Applicant: Agency of Industrial Science and Technology

Claims (1)

[Claims] a first and second cell 7 resetting AND gate;
A master flip-flop current transfer circuit, a slave 7 lip 7U current transfer circuit, and the first cell 7 resetting AND gate is connected to the slave 7
The signal passing through the transistor gate in the second branch of the flip-flop current transfer circuit and the first external input signal are used as input signals, and the AND output signal is used as the AND output signal in the first branch of the mask flip-flop current transfer circuit. The second cell 7 resetting AND gate is the input signal of the Girosefson element gate in the branch of the slave flip 7.
The signal passing through the Sefson element gate in the first branch of the Yotsubu Danryu transfer circuit and the second external input signal are used as input signals, and the logical product outputs the second branch of the master flip-flop current transfer circuit. The master flip 7JL is used as an input signal to the gate of the flip-flop element 7JL in the branch 1.
The Josephson element gates in the first and 20th branches of the current transfer circuit use the output of the $$3 self-resetting AND gate and the clock signal as input signals, respectively. The signal appearing on the branch is used as the input signal of the transfer circuit to the slave frig 70 Tsubuden,
The external Sefson device gates in the first and second branches (I) of the slave flip-flop current transfer circuit are
A tossable logic circuit characterized in that the output signal of the master flip-flop current transfer circuit and the complementary signal of the clock signal are used as input signals, and an AND output is used as an output signal.