JPS6153814A - Latch circuit - Google Patents

Abstract

PURPOSE:To increase the degree of integration by interposing a feedback resistance of high-resistance polysilicon between the output of the 3rd circuit element and the input of the 2nd circuit element, and writing a signal in a latch circuit by the 1st circuit element without spoiling delay characteristics. CONSTITUTION:The feedback resistance 7 uses polysilicon having about 10<5>- 10<7>OMEGA high resistance, so it is realized without requiring a large area on an IC and an about 10MOMEGA value is easily obtained. Therefore, the input resistance of the latch circuit composed of inverters 5 and 6, i.e. equivalent on resistance of the inverter 6 is about 10MOMEGA and sufficiently large. On the other hand, the equivalent on resistance when a clock signl is at H and an inverter 4 is turned on is about 1-10KOMEGA. Therefore, the ratio of resistance values of the both is about 10<6> times, so new data are written in the latch circuit without spoiling delay characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a latch circuit for a static semiconductor integrated circuit constituted by 0-MO8 transistors.

rPrior art] The latch circuit of a conventional static semiconductor integrated circuit is
A circuit using a clocked inverter consisting of a pair of P-channel and N-channel insulated gate capacitive effect transistors as shown in Figure 1, or a circuit using a transmissive gate as shown in Figure 2. is connected to 7'1111 signal line 1, and C to which the clock signal is connected.
It has a signal line 2 and a stone signal line 3 to which an inverted signal of the clock signal is connected, and when the clock signal is "H', the input data is passed through L, and as the clock signal changes from Hf to L1, This is a circuit that latches input data.

[Problem that the invention seeks to solve]

However, since the latch circuit of a conventional static semiconductor integrated circuit requires at least two clocked gates and one inverter, the number of transistors and the number of wires are the limitations, and if the current circuit is used, it will not be possible to use more than two clocked gates and one inverter.
There was a problem in that it was not possible to simply reduce the circuit size on a semiconductor integrated circuit (semiconductor integrated circuit, hereinafter the same).

Therefore, the present invention was developed to solve this problem, and its purpose is to provide a circuit that performs the same latch operation as the conventional one, but with fewer transistors and wires than the conventional one, and therefore a smaller circuit size on the IC. An object of the present invention is to provide a latch circuit for a static semiconductor integrated circuit.

[Means for solving problems]

The latch circuit of the static type medium conductor integrated circuit of the present invention includes a first circuit element that transmits an input signal to the next stage in response to a control signal, and a second circuit that receives the output signal of the first circuit element as an input signal. a conventional circuit that connects an output signal of the third circuit element and an input signal of the second circuit element; The third circuit element has a simple inverter configuration to simplify the circuit element, and at the same time, a feedback resistor using high resistance polysilicon is installed between the output of the 30th circuit element and the input of the second circuit element. The present invention is characterized in that the first circuit element is inserted to facilitate writing into the latch circuit and to increase the degree of integration without impairing delay characteristics.

r effect] According to the above configuration of the present invention, when the control signal is active, the output of the first circuit element and the output of the third circuit element are connected in common, so that the output of the first circuit element is When comparing the equivalent on-resistance of the first circuit element and the equivalent on-resistance of the third circuit element, the former is equal to the equivalent on-resistance of the insulated gate capacitive effect transistor, so it is approximately 1
~10Ω, whereas the latter has a sheet resistance approximately equal to the value of a feedback resistor using polysilicon with a sheet resistance of about 106 to 107Q/hole, so it is possible to easily obtain a value of about 10MΩ. Therefore, the former against the latter
) becomes as large as 106, new input data is written to the latch circuit.

On the other hand, when the control signal is inactive, a latch circuit composed of a second circuit element, a third circuit element, and a feedback resistor using high-resistance polysilicon retains the previous data.

[Example-1] Figure 3 shows an example according to the present invention, where 4 is the first
A clocked inverter is a circuit element.

5 is an inverter which is a second circuit element, 6 is an inverter which is a third circuit element, and 7 is a feedback resistor using high resistance polysilicon.

The feedback resistance of 7 is approximately 10' to 10', Q/e
Since it uses high-resistance polysilicon, it can be implemented without taking up much space on the IC, and a value of about 10 MΩ can be easily obtained. Therefore, the long resistance of the latch circuit composed of the 5 and 6 inverters, that is, the equivalent on-resistance of the 6 inverters, can take a sufficiently large value of about 10 MΩ. on the other hand,
The equivalent on-resistance when the clock signal is "H' and the four tallocked inverters are turned on is about 1 to 1 OKΩ.

Therefore, since the ratio of these two resistance values is about 10', new data can be written into the latch circuit without damaging the delay characteristics. The clock signal is
At Lf, the equivalent on-resistance of the clocked gate 4 is at least about 1 GΩ, which is sufficiently larger than the equivalent on-resistance of the inverter 6, so the latch composed of the inverters 5 and 6 The circuit can retain previous data.

[Example 2] Figure 4 shows two stages of latch circuits according to the present invention connected in series,
This is an embodiment of the present invention, in which a flip-flop circuit is constructed by interchanging the control signals in the first and second stages with their polarity and inverse polarity. 8Vi master side latch circuit,
9 is a latch circuit on the slave side.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and other circuit elements such as a NAND circuit, a NOR circuit, and a composite gate can be considered as the second circuit element or the circuit element of ta3.

61 [Effects of the Invention] As described above, according to the present invention, the number of transistors can be reduced compared to the conventional example, and therefore the number of wiring can be reduced, and the size of the feedback resistance can also be reduced. Since the size can be sufficiently suppressed, the circuit size can be further reduced on the C, and the effect of reducing the degree of integration can be obtained.

[Brief explanation of the drawing]

Figures 1 and 2 are circuit diagrams showing the launch circuit of a conventional static semiconductor memory device, and Figures 3 and 4 are circuit diagrams showing the launch circuit of a conventional static semiconductor memory device.
Each figure is a circuit diagram showing an embodiment of a latch circuit of a static semiconductor memory device of the present invention. 1... D signal line 2 to which the input signal is connected...
...0 signal line 3 to which the Kurotsuta signal is connected...
・When the inverted signal of the clock signal is connected, the signal line 7...Feedback resistor 8...Master side latch circuit 9...Slave side catch circuit and above

Claims (1)

[Claims] In a circuit composed of C-MOS transistors, a first circuit element transmits an input signal to the next stage by a control signal, and an output signal of the first circuit element is used as an input signal, and an inverted signal of the input signal is always output. a second circuit element that takes the output signal of the second circuit element as an input signal and always outputs an inverted signal of the input signal; 1. A latch circuit for a static semiconductor integrated circuit, comprising a feedback resistor made of high-resistance polysilicon that connects input signals of two circuit elements.