JPS60150314A - D flip-flop circuit - Google Patents

Abstract

PURPOSE:To decrease the occupied area of pattern layout by using a high resistance element as a feedback circuit for data storage. CONSTITUTION:A high resistance polycrystal silicon 11 is used as the feedback circuit for data storage. The sheet resistance is several Gohms/square - several tens of Gohms/square and a high resistance load is realized by a small area. When a clock input signal phi is at L in this case, a gate input signal of transistors (TR) 31, 32 is at L. A data output of L level is stored at a data output terminal 6 at this time. It is supposed that the signal phi goes to H and a data signal D of H level is inputted next. The pull-down by a TR41 and the pull-up by the signal D are made reciprocal, but since the resistance value of a feedback circuit 11 is sufficiently larger in comparison with the ON-resistance of the TR31, 32, the TR31 is turned on and the TR41 is turned off and H level is outputted from the terminal 6. When the gate signal of the TRs 31, 32 is at H, the level of the signal phi changes to H and when the signal D of L level is inputted, the L level is outputted from the terminal 6 similarly as above.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a D-flip-flop circuit comprising metal oxide semiconductor (hereinafter referred to as MO3) transistors and operated by a synchronous clock signal. [f? ] Instead of using transmission gates that receive mutually inverted clock signals as gate inputs, high-resistance polycrystalline silicon is used to reduce the pattern size and simplify the circuit configuration.

[Prior art]

Conventionally, D-flip-flop circuits used in MOS integrated circuits such as microprocessors are used for purposes such as data transfer, and a typical circuit configuration thereof is shown in FIG. In the figure, 1 is an N-channel MOS transistor to which a data signal is input to its source or drain, and is turned on by a clock input signal φ input to its gate.

Controlled off. 3.4 is a two-stage cascade-connected MOS)
The transistor-structured inverter (inverting amplifier) 2 is an N-channel type MOS) transistor, which functions as a feedback circuit for feeding back the outputs of the cascade-connected inverters 3 and 4 to its input. An inverted signal φ of the clock signal φ is applied to its gate. 5
6.7 is a data input terminal connected to the source or drain of the MOS transistor 1, and 6.7 is a data output terminal connected to the output of the inverter circuit 4.3.

Next, the operation will be explained.

When the clock input signal φ becomes "I", the MOS transistor 1 is turned on and a data signal is input from the data input terminal 5. This data signal is output as an output signal Q from the data output terminal 6 via the two imparks 3.4.

In addition, from the data output terminal 7, the output of the inverter 3,
That is, a signal stone that is an inversion of the data signal is output. At this time, the gate L- of the N-channel MO3+- transistor 2 receives an inverted signal φ(“
'L'') is applied, and the MO3+- transistor 2
is in the off state.

Next, when the clock input signal φ becomes “L”, the MOS)
Since the gate input signal T of the transistor 2 becomes "1-11", the MO3I transistor 2 is turned on and the input data signal is held.

FIG. 2 shows a timing diagram of the D-Frinobuf one-chip circuit shown in FIG. 1. At the rising edge of the input clock signal φ, the input data signal is outputted as the output signal Q. Then, the output signal Q is held until the next rising edge of the clock signal. In this way, in order to realize a D-flip-flop circuit, two types of clock signals φ and T, which are inverted to each other, were conventionally required. Figure 3 shows a D-flip-flop circuit that operates with a single clock signal. An example of a circuit is shown. Instead of the MO3+- transistor 2 in FIG. 1, a depletion transistor 9.
10 is used to construct a D-flip-flop circuit. That is, the depletion transistors 9 and 10 are connected in series to generate a high resistance load to hold the data signal. However, in such a circuit configuration, although only a single input clock signal is required, the number of 1-transistors is greater than that of the D-flip-flop circuit shown in FIG.

As described above, the conventional D-flip-flop circuit shown in FIGS. 1 and 3 has the disadvantage that the area occupied by the circuit is large due to its pattern layout.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above.
In a flip-flop circuit, by using a high resistance element as a feedback circuit for data retention, the area occupied by the flip-flop circuit can be reduced in terms of pattern layout.
- Aims to provide flip-flop circuits.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 shows a D-flip-flop circuit according to an embodiment of the present invention, in which the same reference numerals as in FIGS. 1 and 3 indicate the same components. In this embodiment, a high-resistance metal is used as a feedback circuit for data retention, that is, in place of the N-channel MOS transistor 2 in the conventional example shown in FIG. 1, and the depletion transistors 9 and 10 shown in FIG. High resistance polycrystalline silicon in a certain undoped state 1
1 is used. This high-resistance polycrystalline silicon has a sheet resistance of several 007 to several tens of 097, and can realize a high resistance load with a small layout area.

Figure 5 shows the circuit in Figure 4 in more detail, with 31
．． 32 and 41.42 are N-channel type and P-channel type MOS transistors forming the inverter 3.4, respectively.

Next, the operation will be explained using FIG. 5.

Now, when the clock input signal φ applied to the gate of MOS transistor 1 is "L", the gate input signals of transistors 31 and 32 are "L". At this time, "L" data output is held from the data output terminal 6.

Next, assume that the gate input signal φ becomes "tr" and a data signal of "H" is input from the data input terminal 5. At this time, the pull-down by the transistor 41 and the pull-up by the input data signal are in a contradictory state. However, since the resistance value of the high-resistance polycrystalline silicon 11 serving as the feedback circuit is sufficiently larger than the on-resistance of the transistors 31 and 32, this turns the IQN channel type transistor 31 into the on state and turns the P channel type transistor into the on state. 41 is turned off, and the output signal Q from the data output terminal 6 is “H”.
is output.

Next, the gate signals of transistors 31 and 32 are “■(”
, the gate signal φ of transistor 1 changes from “L” to “H”, and “
Suppose that a data signal of L'' is input. At this time, the pull-amplification by the transistor 42 and the pull-down by the input data signal are in a contradictory state, but as described above, the high-resistance polycrystalline silicon 11 causes the transistors 31.3 to
The gate input signal of 2 becomes “L”, and the data output terminal 6
An "L" signal is output from.

In the circuit of this embodiment, the feedback circuit for data retention is constructed using high-resistance polycrystalline silicon, so the area occupied by the circuit on the pattern layout can be made much smaller than in the past, and the circuit configuration can be further simplified. can be easily done.

〔Effect of the invention〕

As described above, according to the present invention, a high-resistance element is used as a feedback circuit for feeding back the output of a multi-stage inverting amplifier to its input in a D-flip-flop circuit composed of MO3I-transistors. This has the effect of reducing the area occupied above and enabling a highly integrated circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a configuration example of a conventional D-flip-flop circuit, FIG. 2 is a timing chart diagram for explaining the operation of the circuit, and FIG. 3 is a diagram showing a conventional D-flip-flop circuit using a depletion transistor. FIG. 4 is a circuit diagram of a D-flip-flop circuit according to an embodiment of the present invention, and FIG. 5 is a more detailed circuit diagram of the circuit. 3, inverter (inverting amplifier), 11... high resistance element. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 3 Figure 4 Figure 5 Figure 11 Procedural amendment (voluntary) 1. Indication of case Japanese Patent Application No. 59-7547 3. Person making the amendment Relationship with the case Patent applicant Address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name:
(601) Mitsubishi Electric Corporation Representative Katayuni Hachibe 4, Agent address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo, '1.
5. Claims column of the specification to be amended and Detailed description of the invention column 6. Contents of the amendment (1) The claims of the specification are corrected as shown in the attached sheet. (2) Correct "undoped high-resistance polycrystalline silicon, which is a high-resistance metal" to "high-resistance polycrystalline silicon" in Mei 8m, page 5, lines 18-19. (3) In the 3rd and 4th lines of page 8, ``Since multiple stages... were used,'' was changed to ``as a feedback circuit that feeds back the output of an even number of cascaded inverting amplifiers to its input.'' Since we used high-resistance polycrystalline silicon as a resistance element, we corrected it to ``. Claims fi+ A D-flip-flop circuit consisting of a metal-oxide semiconductor transistor, comprising a large inverting amplifier connected in series with Bl'i and Jl, and a high-resistance element, and an even-numbered group U circuit connected in parallel with Bl'i and Jl. 1. A D-flip-flop circuit comprising a feedback circuit for feeding back the output of an inverting amplifier to its input. (The high-resistance elements constituting the feedback circuit in Section 21l.
The Il-flip-flop circuit according to claim 1, characterized in that the Il-flip-flop circuit is made of famous crystalline silicon with anti-J"1Σ"lfl.

Claims (1)

[Claims] (11) A D-flip-flop circuit consisting of metal oxide film semiconductor transistors, comprising a plurality of cascade-connected inverting amplifiers and a high resistance element, the output of the plurality of inverting amplifiers being connected in series. A D-flip-flop circuit comprising a feedback circuit that feeds back to an input. (2) A high resistance element constituting the feedback circuit is polycrystalline silicon. D-flip-flop circuit according to item 1.