JPS62196923A - Cmos logic gate - Google Patents

Abstract

PURPOSE:To decrease the number of FETs with no change of logic and to reduce the pattern area of an IC by sharing both p and n type FET which use the data signals as inputs to plural clock gates which use the same data signal as the input and works with clocks of the same phase. CONSTITUTION:The p channel type transistors TR31 and 32 which use the clock signal, the inverse of phi as the gate input. While a p channel type TR34 is set between a common terminal 33 which connects in common the single ends of both TR31 and 32 with each other and a power supply 19 and uses the data signal as the input. Furthermore the n channel TR35 and 36 use the clock signal phi as the gate input and an n channel type TR38 is set between a common terminal 37 which connects in common the single ends of both TR35 and 36 and the earth and uses the data signal as the gate input respectively. Then both joints 7 and 9 are defined as the logic output parts. Both p and n channel type FET which use the data signals as gate inputs are shared to plural clocked gates which use the same gate signal as gate inputs. Thus the number of FETs can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION (Industrial Field of Application) The present invention relates to 0MO8 (complementary MO8) logic f-) using a clock clock.

(Prior art) Conventionally, CMOS logic f-) using clocked gates
, in a frizzo flop circuit, each clocked gate receives a data signal as input for each clocked gate f-).
It consisted of four or more FETs (field effect transistors) of channel type and N-channel type. Figure 3 is for explaining this.
) is a D-flip flop circuit, and (b) is a D-flip flop circuit.
) is a clocked inverter circuit diagram corresponding to the dotted line, 1 to 4 are clocked inverters, 5 and 6 are inverters, 7 to 10 are nodes, φ and ¥ are clock signals having an inverted relationship with each other, and D is a data input, and Q and Q are flip-flop outputs. Also, 11 to 14 are P-channel FETs.
, 75 to 18 are N-channel FETs, and I9 is a power supply. That is, as shown in FIG. 3(b), P channel type transistors 11 to 14 and N channel type transistors 15 to 1
8 transistors were required.

Figure 4 shows a clear type flip-flop using clocked gates, 21 in the figure is a clocked inverter,
22 to 24 are clock donand circuits, 25 and 26 are inverters, CD is a clear terminal, and 51 to 54 are nodes. In this case as well, the clock donand circuits 22 and 23 within the dotted lines have the same problem as in the case of FIG. 3 above.

(Problems to be Solved by the Invention) Therefore, the present invention provides a 0MO8 using a clocked r-).
Fewer FETs in logic gates than in conventional circuits
The present invention is intended to provide a 0MO8 logic gate that can be configured in numbers.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a plurality of P-type FETs whose gate input is a first clock signal, a first common terminal in which one ends of the FETs are commonly connected, and a first A P-type FET configured between a power supply and having a data signal as a gate input, a plurality of N-type FETs having a second clock signal which is an inversion of the first clock signal as a gate input, and one end of the FET. This device includes an N-type FET which is configured between a second common terminal that is commonly connected to each other and a second power source, and which receives a data signal as a gate input.

(Function) The present invention provides an 0MO8 logic gate including a clocked gate, in contrast to a plurality of clocked gates that use the same data signal as gate input, a P-channel type and an N-channel type that use a data signal as gate input. By sharing the FIT, the number of FETs that input the data signal, which was conventionally required for each data signal, can be reduced, and a CMOS logic circuit can be configured with fewer FETs than before. This is how it was done.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram of the same embodiment, and the circuit within the dotted line in FIG. 3(a) is realized according to the present invention. That is, this configuration includes P-channel transistors 31 and 32 that receive a clock signal φ as a gate input, and a P-channel transistor that is configured between a common terminal 33 whose ends are commonly connected to each other and the power supply 19 and that receives a data signal as a gate input. Channel type transistor 3
N-channel transistors 35 and 36 are provided, each of which receives a clock signal φ as a gate input, and is configured between a common terminal 3'7 whose one end is commonly connected to the ground, and which receives a data signal as a gate input. A channel type transistor 38 is provided, and connection points 7 and 9 are used as logic output sections.

In FIG. 3 (,), the clock signal φ is “H# (high)”.
When the level is set, clocked inverter 2.3 is turned on, and data at node 8 is transmitted to node 7.9. Further, the data at node 7.8 is latched by inverter 5 and clocked inverter 3. At this time, considering the state of the transistors in the clocked inverter 2.3, in FIG.
Since the transistors 35, 36, 31, and 32 to which φ is input are on, the transistor 34 or 38 connects the power supply 19 (positive power supply VDD) according to the data at the node 8.
) or ground (negative power supply Vss) potential is transmitted to nodes 7 and 9, respectively.

Next, considering the time when the clock signal φ becomes L'' (low) level, in FIG. 3(a), the clocked inverter 1
, 4 are turned on, and the data signal is connected to nodes 7 and 8.
The data at nodes 9 and 10 are latched by inverter 6 and clocked inverter 4. At this time, even if the data at nodes 7 and 9 are at opposite levels, as shown in FIG. Therefore, there will be no short circuit, and the circuit will not malfunction.

FIG. 2 shows the present invention implemented in a clear type flip-flop circuit, and the portion surrounded by the dotted line in FIG. 4 is shown as transistors 41 to 48.

By doing so, the number of transistors in the circuit shown in FIG. 1 can be reduced by two compared to the conventional circuit. Furthermore, in the circuit shown in FIG. 2, it is possible to reduce the number of transistors/disasters by four.

(Effects of the Invention) According to the present invention, in a logic circuit including a plurality of clocked gates, a data signal is input to a plurality of clocked gates that receive the same data signal and operate with clocks of the same phase. Since the P-type and Nfi FITs are shared, the logic does not change (the number of FETs can be reduced. Therefore, the integrated circuit pattern area can be reduced compared to the conventional one. Also, like the y-door array, In the case of a method of configuring a circuit using FETs with predetermined dimensions, reducing the number of FITs directly leads to a reduction in the number of basic circuit cells that make up the logic circuit.
This is an even greater advantage.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of embodiments of the present invention. Figure 3 (,) is a D-type flip-frog circuit diagram;
) is a partial detailed circuit diagram of the same circuit, and Figure 4 is a clear type flip-flop circuit diagram. 8...r-evening signal input node, 7,9...data signal output node, I9...power supply, 31.32.3'4°41-44...P-type FET, 35.36. 38.45
~48...N type FIST. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] Multiple P-type Fs with the first clock signal as gate input
ET, a P-type FET which is configured between a first common terminal in which one ends of the FETs are commonly connected and a first power supply and receives a data signal as a gate input; A plurality of N-type FETs each having a clock signal of 2 as a gate input, and an N-type FET having a data signal as a gate input. type FET, and each connection between the other end of the plurality of P-type FETs and the other end of the plurality of N-type FETs is a logic output part. .