JPH0220015B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a Josephson logic circuit, and more particularly to a J-K flip-flop circuit constructed using Josephson elements.

(2) Background of the technology With the development of information processing technology, information processing devices such as electronic computers are becoming faster and larger in capacity.

Attempts have been made to apply a so-called Josephson device that utilizes superconductivity as one of the functional elements constituting such an information processing device.

Such a Josephson device has the feature that it can operate at higher speeds than devices using semiconductor materials such as silicon or gallium/arsenic.

(3) Prior Art and Problems A JK flip-flop circuit, which is one of the logic circuits constructed using Josephson elements as functional elements, has a conventional structure as shown in FIG.

In the same figure, J ₁ to J ₁₀ are Josephson elements,
R ₁ to R ₁₂ are resistances, and L is inductance. Further, Vac ₁ to _{Vac 4} are AC bias current sources, and DC is a DC current source.

In such a J-K flip-flop circuit, for example, when the critical current of Josephson element J ₃ is suppressed, that is, when the signal current of Josephson element J ₃ is output (inactive state), the input When a signal current is applied to the terminal J _IN , the Josephson element J ₁ is rendered inactive.

Therefore, the current from the bias current source Vac ₁ flows through the resistors R ₁ and R ₃ and further through the resistor R ₇ to the reference potential (ground potential). As a result, Josephson element _J5 is rendered inactive. By making Josephson element _J5 inactive, the current from DC current source DC flows through Josephson element _J6 . Therefore, Josephson element J ₈ is brought into an inactive state, and therefore Josephson element J ₉ is brought into a superconducting state.

On the other hand, since Josephson element J ₅ is in an inactive state, Josephson element J ₇ is in a state where the critical current is not suppressed (active state), and therefore Josephson element J ₁₀ is in an inactive state.

Therefore, the current from bias current source Vac ₇ passes through resistor 12 and converts Josephson element J ₄ into an inactive state. Also, the current from the bias current source Vac ₃ flows through Josephson element J ₇ to the reference potential.

As a result, an output is taken out from the output terminal Jout (Q).

When a signal current is applied to the input terminal K _IN , the same operation as above is performed and the output terminal KOUT
Output is taken from Q.

In such a JK flip-flop circuit, since the circuit is constructed by combining a latching gate and a flip-flop, it is impossible to reset the latching gate unless an alternating current bias current is applied. Can not. Therefore, two types of current sources, a DC power source and an AC power source, are required.

Furthermore, since the resistors R ₁ to _{R 12} are included, the manufacturing process becomes complicated, leading to a decrease in manufacturing yield and reliability.

(4) Purpose of the Invention The present invention eliminates the problems with the conventional J-K flip-flop circuit, can operate with only a DC power supply, and is composed only of a current transfer circuit without a resistive element. A JK flip-flop circuit is provided.

(6) Structure of the Invention Therefore, according to the present invention, first and second Josephson gates J 101 whose one ends are commonly connected in parallel to the first bias input terminal Ib to form a first loop are provided _. , J ₁₀₂ , and third and fourth Josephson gates J having one end commonly connected in parallel to the second bias input terminal Ia to form a second loop. ₁₀₄ ,
Second self-resetting AND consisting of J ₁₀₅
gate, and a fifth gate whose one end is commonly connected in parallel to the third bias input terminal Ic to form a third loop.
and a master flip-flop current transfer circuit consisting of a sixth Josephson gate J ₁₀₃ and J ₁₀₆ , and a fourth The 7th and 8th Josephson gates forming the loop J ₁₀₇ , J ₁₀₈
The first Josephson gate _J101 has a current flowing through a branch on the eighth Josephson gate side of the fourth loop and an opposite current flowing through the branch on the eighth Josephson gate side of the fourth loop. It is input as a control line input of DC current flowing in the direction,
The first Josephson gate is in an inactive state as long as only the direct current flows, and the second Josephson gate J ₁₀₂ has a current on the side of the eighth Josephson gate of the fourth loop. The current flowing through the branch of the second Josephson gate and the first external signal current K flowing in the same direction as the control line input are input as control line inputs, and the second Josephson gate becomes inactive, and the third Josephson gate J ₁₀₄ has the fourth
The current flowing through the branch on the seventh Josephson gate side of the loop and the direct current flowing in the opposite direction.
The third Josephson gate is inactive only when DC is input as the control line input and only the DC current is flowing, and the fourth Josephson gate J ₁₀₅ has the fourth A current flowing through a branch on the seventh Josephson gate side of the loop and a second external signal current J flowing in the same direction as the current are input as control line inputs, and currents are flowing in both of the two control line inputs. Only when the fourth Josephson gate is inactive, the fifth Josephson gate J ₁₀₃ has a current flowing through the branch on the first Josephson gate side of the first loop and A first clock signal current flowing in the same direction as the first clock signal current is input as a control line input, and the fifth clock signal current flows in the same direction as the first clock signal current.
The Josephson gate of J 106 becomes inactive, and the current flowing through the branch on the third Josephson gate side of the second loop and the current flowing in the same direction as the sixth Josephson gate J ₁₀₆ become inactive. The sixth Josephson gate is inactive only when the first clock signal current C is input as a control line input, and current is flowing in both control line inputs, and the seventh clock signal current C is inactive. Josephson Gate J ₁₀₇
A current flows through a branch on the fifth Josephson gate side of the third loop, and a second current flows in the same direction as the branch on the fifth Josephson gate side, and a second current flows through the branch when the first clock signal current C does not flow. The clock signal current is input as a control line input, and only when current is flowing through both of the two control line inputs, the seventh
The Josephson gate becomes inactive, and the current flows through the eighth Josephson gate J ₁₀₈ in the same direction as the current flowing through the branch on the sixth Josephson gate side of the third loop. The second clock signal current is input as a control line input, and the eighth Josephson gate is inactive only when current is flowing in both control line inputs, and the fourth clock signal current is inputted as a control line input. A Josephson logic circuit is provided which features an output signal.

Hereinafter, the present invention will be explained in detail using examples.

(7) Embodiments of the Invention FIG. 2 shows a JK flip-flop circuit according to the present invention.

In the same figure, J ₁₀₁ to J ₁₀₈ are Josephson elements,
RS ₁ and SR ₂ are self-resetting AND gates,
M is a master flip-flop current transfer circuit;
S is a slave flip-flop current transfer circuit;
Vac ₁ to Vac ₄ are bias current sources.

Here self-resetting AND gate SR ₁
In this case, the input signal to the input terminal K _IN and the output of the slave flip-flop current transfer circuit S
In the case of the self-resetting AND gate _SR2 , the input signal to the input terminal JIN is ANDed with the output Qout of the master flip-flop current transfer circuit M.

Further, the master flip-flop current transfer circuit M is driven by an external clock signal C, and the slave flip-flop current transfer circuit S is driven by an inverted signal of the clock signal current C.

The master flip-flop current transfer circuit M is controlled by the output signals of the self-resetting AND gates SR ₁ and SR ₂ , and the slave flip-flop current transfer circuit S is controlled by the output signals of the self-resetting AND gates SR 1 and SR 2.
Its state is set by the state of the master flip-flop current transfer circuit M.

That is, for example, when the output is at a high level and Qout is at a low level, when an input signal pulse J is applied to the input terminal J _IN in synchronization with the clock signal C, a DC offset current DC is applied. The bias current flowing through the Josephson device J ₁₀₅ due to the presence of the Josephson device J ₁₀₄ , which is now inactive, is transferred to the Josephson device by the input signal pulse J and the output of the slave flip-flop current transfer circuit S. J _-105
becomes inactive and flows to Josephson element J ₁₀₄ .

Note that the amount of current flowing through Q _put , input signal pulse J, and DC offset current DC is approximately equal, and the amount of current of Q _put and input signal pulse J is such that even if one of them is turned on, the Josephson gate
J ₁₀₅ cannot be inactive, but it is set to a value that allows the Josephson gate J ₁₀₅ to be inactive when both are on. In addition, since the control line through which the DC offset current DC flows is wound twice, the magnetic field that the DC offset current DC gives to the Josephson gate _J104 changes when both the Q _put and the input signal pulse J are turned on. It is approximately equal to the magnetic field applied to Josephson Gate J ₁₀₅ .
As described above, the relationship between the amount of current input to the control line is the same for the self-resetting AND gate SR.

Furthermore, Josephson gates J ₁₀₃ , J ₁₀₆ , J ₁₀₇ , and J ₁₀₈ are each magnetically coupled with two control lines through which current flows in the same direction; If current is passed through the control line, the Josephson gate will not become inactive, but if current is passed through both control lines, a current of such magnitude as to make the Josephson gate inactive will flow.

Due to the current flowing through the Josephson element J ₁₀₄ and the clock signal C, the Josephson element J ₁₀₆ in one branch of the master flip-flop current transfer circuit M is inactivated, and the bias current source
The bias current flowing from Ic flows through Josephson element J ₁₀₃ of the other branch, flows into the slave flip-flop current transfer circuit S, and flows to the reference potential (ground potential).

Then, in synchronization with clock signal C, the input terminal
When an input signal pulse K is applied to K _IN , the bias current flowing through the Josephson element 102 due to the Josephson element 101, which has been made inactive by the DC offset current DC, is reduced by the input signal pulse K. The output Qout of the slave flip-flop current transfer circuit S causes Josephson element J ₁₀₂ to become inactive, so that the current flows to Josephson element J ₁₀₁ .

Due to the current flowing through the Josephson element J ₁₀₁ and the clock signal C, the Josephson element ₁₀₃ of the other branch in the master flip-flop current transfer circuit M is rendered inactive, and the bias current flowing from the bias current source Ic is The current flows through Josephson element J ₁₀₆ of one branch and flows into the slave flip-flop current transfer circuit S, where it flows to the reference potential.

The master flip-flop current transfer circuit M
The Josephson device J ₁₀₃ is deactivated by the output of the clock C and the inverted signal of the clock C, and the bias current Ia flows through the Josephson device J ₁₀₇ and the slave flip-flop current transfer circuit S.
The output of is .

Furthermore, when input signal pulses are simultaneously applied to the input terminals K _IN and J _IN , the self-resetting AND gate SR ₁ ,
or SR ₂ is output to invert the master and slave flip-flop current transfer circuits M and S, respectively.

The JK flip-flop circuit according to the present invention shown in FIG. 2 is expressed by logic symbols as follows:
It is expressed as shown in FIG.

Further, the operation of the JK flip-flop circuit according to the present invention is expressed using a timing chart as shown in FIG.

In the embodiment of the JK flip-flop circuit according to the present invention, the case where the clock signal C is applied externally has been disclosed, but the present invention is not limited to this. For example, by providing the self-resetting inverter circuit shown in FIG. 5 within the Josephson integrated circuit in which the JK flip-flop circuit is formed, the clock signals C, C can be generated within the Josephson integrated circuit. can. In the same figure,
J ₅₀₁ and J ₅₀₂ are Josephson devices, and Cout is an externally applied clock signal.

(8) Effects of the Invention According to the present invention as described above, a J-K flip-flop circuit using Josephson elements can be constructed only by a current transfer circuit. Therefore, there is no need to use a resistor as in the prior art, the number of Josephson elements can be reduced, and furthermore, there is no need to use an AC bias power supply, so the Josephson circuit including the J-K flip-flop circuit can be Improving the degree of integration of integrated circuit devices,
Manufacturing yield can be improved.

[Brief explanation of drawings]

Figure 1 is a wiring diagram showing the configuration of a conventional J-K flip-flop circuit, and Figure 2 is a J-K flip-flop circuit according to the present invention.
FIG. 2 is a wiring diagram showing the configuration of a flip-flop circuit. FIG. 3 is a block diagram showing the logical configuration of the JK flip-flop shown in FIG. 2, and FIG. 4 is a timing chart showing the operating state of the JK flip-flop circuit. Further, FIG. 5 is a wiring diagram showing an example of a clock signal generation circuit applied to generate a clock signal inside the Josephson integrated circuit device. In the figure, J ₁ to J ₁₀ , J ₁₀₁ to _{J 108} and J ₅₀₁ , J ₅₀₂
is a Josephson element, R ₁ to R ₁₂ are resistances, and L is an inductance. Further, SR is a self-resetting AND gate, M is a master flip-flop current transfer circuit, and S is a slave flip-flop current transfer circuit.

Claims (1)

[Claims] 1. A first gate comprising first and second Josephson gates J ₁₀₁ and J ₁₀₂ whose ends are commonly connected in parallel to the first bias input terminal Ib to form a first loop.
A self-resetting AND gate, and third and fourth Josephson gates J ₁₀₄ and J ₁₀₅ whose one ends are commonly connected in parallel to the second bias input terminal Ia to form a second loop. It consists of two self-resetting AND gates, and fifth and sixth Josephson gates _J103 and _J106 , one end of which is commonly connected in parallel to the third bias input terminal Ic to form a third loop. a master flip-flop current transfer circuit; and seventh and eighth Josephson gates, one end of which is commonly connected in parallel to the other ends of the fifth and sixth Josephson gates to form a fourth loop. A slave flip-flop current transfer circuit consisting of J ₁₀₇ and J ₁₀₈ is provided, and the first Josephson gate J ₁₀₁ has a branch of the fourth loop on the eighth Josephson gate side. A flowing current and a direct current DC flowing in the opposite direction are input as control line inputs, and as long as only the direct current is flowing, the first Josephson gate is in an inactive state, and the second Josephson gate is in an inactive state. _J102 includes a current flowing through the branch on the eighth Josephson gate side of the fourth loop and a first current flowing in the same direction as the branch on the eighth Josephson gate side.
An external signal current K is input as a control line input,
The second Josephson gate is inactive only when current flows in both the two control line inputs, and the third Josephson gate J ₁₀₄ has the seventh control line input of the fourth loop. The current flowing through the branch on the Josephson gate side and the DC current DC flowing in the opposite direction are input as control line inputs, and the third Josephson gate is inactive only when only the DC current is flowing. state, and the fourth Josephson gate J ₁₀₅ has a current flowing through the branch on the seventh Josephson gate side of the fourth loop and a second current flowing in the same direction as the current flowing through the branch on the seventh Josephson gate side of the fourth loop.
The external signal current J is input as a control line input,
The fourth Josephson gate is inactive only when current flows in both of the two control line inputs, and the fifth Josephson gate J ₁₀₃ has the first The current flowing through the branch on the Josephson gate side and the first flowing in the same direction as the
A clock signal current of J is input as a control line input, and the fifth Josephson gate becomes inactive only when currents are flowing in both of the two control line inputs, and the sixth Josephson gate J ₁₀₆ , the current flowing through the branch on the third Josephson gate side of the second loop and the first clock signal current C flowing in the same direction as the current are input as control line inputs, and the two control lines The sixth Josephson gate is inactive only when current is flowing in both line inputs, and the seventh Josephson gate _J107 has a fifth Josephson gate of the third loop. A current flowing through the branch on the gate side and a second clock signal current flowing in the same direction as the current and flowing when no current is flowing in the first clock signal current C are input as control line inputs, and the two controls The seventh Josephson gate is inactive only when current is flowing in both line inputs, and the eighth Josephson gate J ₁₀₈ has a sixth Josephson gate of the third loop. The current flowing in the branch on the gate side and the second clock signal current flowing in the same direction as the current are input as control line inputs, and the eighth clock signal current flows only when currents are flowing in both the two control line inputs. A Josephson logic circuit characterized in that the song gate is inactive and an output signal is taken out from the fourth loop.