JPH05227007A - Interface circuit - Google Patents

Abstract

PURPOSE:To exactly transmit a signal from a semiconductor circuit to a Josephson circuit by means of a simple constitution without lossing the high speed performance of a Josephson element by constituting this interface circuit only of Josephson logical gates. CONSTITUTION:A clock CK is '0', both outputs from an inverter 11 and a non-inversion gate 12 are '1' and both outputs from two-input AND gates 13, 14 are '0'. When the CK is raised to '1', a sub-adjusting clock JCK1 is also raised to '1', and if the level of data SD is '1', the level of data JD1 is also raised in accordance with the CK. When the inverter 11 is in a driven state and the gate 12 is turned to a driven state, the JCK1 falls. During the '1' state of the CK, the output of the gate 12 is '0' and the JCK1 is held at '0' until the CK is raised next. Thereby the Josephson circuit receives the data JD1 corresponding to the data SD only once correspondingly to one CK outputted from the semiconductor circuit and overlappedly reads out the data SD correspondingly to one CK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit for accurately transmitting a signal from a semiconductor circuit using a semiconductor element to a Josephson circuit using a Josephson junction element.

[0002]

2. Description of the Related Art Since Josephson devices operate at high speed and consume low power, a high speed processor using them can be realized.

Conventionally, in the operation experiment of the Josephson circuit,
This is done by generating a signal pattern for the Josephson circuit using a signal generator composed of a semiconductor circuit and transmitting this to the Josephson circuit.

Since the Josephson logic gate performs a latching operation, it is AC biased and reset every clock. On the other hand, since the semiconductor logic gate is DC biased, it is not reset every clock. In addition, in order to take advantage of the high speed performance of the Josephson device, it is necessary to operate the Josephson circuit with a clock faster than the semiconductor circuit. For this reason, if the output of the semiconductor circuit is directly transmitted to the Josephson circuit, the Josephson circuit receives the data in the same clock from the semiconductor circuit in duplicate and malfunctions.

Therefore, as the speed of the Josephson circuit has increased, an interface circuit has been connected between the semiconductor circuit and the Josephson circuit.

[0006]

However, the conventional interface circuit has a complicated circuit structure because it uses a special control device or performs special processing on a signal. Further, the interface circuit using the semiconductor element and the Josephson element cannot fully utilize the high performance of the Josephson element.

In view of such problems, an object of the present invention is an interface capable of accurately transmitting a signal from a semiconductor circuit to a Josephson circuit with a simple structure without impairing the high speed performance of the Josephson element. To provide a circuit.

[0008]

The interface circuit according to the present invention will be described with reference to the reference numerals of corresponding components in the drawings. This interface circuit is for accurately transmitting a signal from a semiconductor circuit using a semiconductor element to a Josephson circuit using a Josephson junction element.

In the interface circuit of the first invention, for example, as shown in FIG. 1, the output end of the first gate 11 is connected to the input end of the second gate 12, and the output end of the second gate 12 is the first AND gate 13. Connected to one input end of
The input end of the first gate 11 is connected to the other input end of the AND gate 13, and the output end of the first AND gate 13 is the second end.
It is connected to one input terminal of the AND gate 14.

The first gate 11, the second gate 12, the first AND gate 13 and the second AND gate 14 are Josephson logic gates. One of the first gate 11 and the second gate 12 is an inverter and the other is a non-gate. It is an inverting gate.

First gate 11, second gate 12 and first gate
Three-phase offset AC bias currents φ1, φ2, and φ3 are supplied to the power input terminals of the AND gate 13, respectively. The phase difference between φ1 and φ2 and the phase difference between φ2 and φ3 are both 120 °. The AC input bias current φ1 or φ3 with offset is supplied to the power supply input terminal of the second AND gate 14, the clock CK is supplied from the semiconductor circuit to the input terminal of the first gate 11, and the other of the second AND gate 14 is supplied. The data SD is supplied to the input terminal from the semiconductor circuit, and the outputs of the first AND gate 13 and the second AND gate 14 are clocks J for reading the data JD, respectively.
It is supplied to the Josephson circuit as CK and data JD.

FIG. 4 shows an embodiment of the first invention, in which the first gate is a non-inverting gate 12 and the second gate is an inverter 11.

The first gate 11 is in an operating state (a bias range of φ1, in other words, a power-on state) and transfers the clock CK to its output terminal, and the clock CK is transferred to the second gate 12 by the phase difference between φ2 and φ3. The data is sequentially transferred to the first AND gate 13. The output of the first AND gate 13 becomes "1" because the data transferred to the first gate 11, the second gate 12, and the first AND gate 13 is "1", and the first AND gate is This is limited to the case where 13 is in the operating state and the clock CK is '1' at the same time.

From this, the output of the first AND gate 13 becomes "1" only in the bias range of .phi.3 which comes first after the clock CK changes from "0" to "1". φ3
This is also the case when the clock CK changes from '0' to '1' in the bias range of, and in this case, in the portion within the bias range after the clock CK changes from '0' to '1'. The output of the 1-and-gate 15 becomes "1".

In the interface circuit of the second invention, for example, as shown in FIG. 5, the output end of the first gate 12A is connected to the input end of the second gate 12B, and the output end of the second gate 12B is connected to the third gate 11. It is connected to the input terminal, the output terminal of the third gate 11 is connected to one input terminal of the first AND gate 13, and the first input terminal is connected to the other input terminal of the first AND gate 13.
The input terminal of the gate 12A is connected to the first AND gate 1
The output end of the third AND gate 3 is connected to one input end of the second AND gate 14.

The first gate 12A, the second gate 12B, the third gate 11, the first AND gate 13 and the second AND gate 14 are Josephson logic gates, and the first gate 12A, the second gate 12B and the third gate 12A. Gate 1 of 1
One is an inverter and the other two are non-inverting gates.

Three-phase offset AC bias currents φ1 at the power source input terminals of the first gate 12A, the second gate 12B, the third gate 11 and the first AND gate 13, respectively.
φ2, φ3 and φ3 are supplied. The phase difference between φ1 and φ2 and the phase difference between φ2 and φ3 are both 120 °. The AC bias current φ1 or φ3 with an offset is supplied to the power input terminal of the second AND gate 14, and the first gate 12
The clock CK is supplied from the semiconductor circuit to the input terminal of A, the data SD is supplied from the semiconductor circuit to the other input terminal of the second AND gate 14, and the first AND gate 13 is supplied.
And the output of the second AND gate 14 is the data JD.
Is supplied to the Josephson circuit as a clock JCK and data JD for reading.

In the interface circuit of the third invention, for example, as shown in FIG. 6, the output end of the first gate 11 is connected to the input end of the second gate 12, and the output end of the second gate 12 is one of the AND gates 13. Is connected to the input end of.

The first gate 11, the second gate 12 and the AND gate 13 are Josephson logic gates. One of the first gate 11 and the second gate 12 is an inverter and the other is a non-inverting gate.

AC bias currents φ1, φ2, and φ3 with offsets of three phases are supplied to the power source input terminals of the first gate 11, the second gate 12, and the AND gate 13, respectively. The phase difference between φ1 and φ2 and the phase difference between φ2 and φ3 are both 120 °. The clock CK is supplied from the semiconductor circuit to the input end of the first gate 11, and the AND gate 1
The data SD is supplied from the semiconductor circuit to the other input terminal of 3, and the outputs of the second gate 12 and the AND gate 13 are supplied to the Josephson circuit as a clock JCK and a data JD for reading the data JD, respectively. However, the data SD must be a signal that returns zero in synchronization with the clock CK, that is, the data SD must be a signal that falls in synchronization with the fall of the clock CK when it is at a high level.

FIG. 7 shows an embodiment of the third invention, in which the first gate is the non-inverting gate 12 and the second gate is the inverter 11.

In the interface circuit of the fourth invention, for example, as shown in FIG. 8, the output end of the first gate 12A is connected to the input end of the second gate 12B, and the output end of the second gate 12B is connected to the third gate 11. It is connected to the input end, and the output end of the third gate 11 is connected to one input end of the AND gate 13.

The first gate 12A, the second gate 12B, the third gate 11 and the AND gate 13 are Josephson logic gates, and the first gate 12A and the second gate 12 are included.
One of the B and third gates 11 is an inverter and the other two are non-inverting gates.

AC bias currents φ1 and φ of three phases are respectively provided at power input terminals of the first gate 12A, the second gate 12B, the third gate 11 and the AND gate 13.
2, φ3 and φ3 are supplied. The phase difference between φ1 and φ2 and the phase difference between φ2 and φ3 are both 120 °. First
A clock C is input from the semiconductor circuit to the input terminal of the gate 12A.
K is supplied, data SD is supplied from the semiconductor circuit to the other input terminal of the AND gate 13, and the third gate 11
The outputs of the AND gate 13 are supplied to the Josephson circuit as a clock JCK and data JD for reading the data JD, respectively. However, this data SD
Is a signal that returns to zero in synchronization with the clock CK,
That is, the data SD must be a signal which falls at the high level in synchronization with the fall of the clock CK.

In any of the above-mentioned first to fourth inventions, since the semiconductor logic gate is not used and only the Josephson logic gate is used, the high speed performance of the Josephson device is not impaired. Further, in any of the first to fourth inventions, no special control device is used or no special processing is applied to the signal, and the signal is accurately transmitted from the semiconductor circuit to the Josephson circuit with a simple configuration. be able to.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 shows an interface circuit 10 of the first embodiment. This interface circuit 1
0 is connected between the semiconductor circuit and the Josephson circuit, and is for accurately transmitting the signal output from the semiconductor circuit to the Josephson circuit. For high speed operation, the interface circuit 10 is configured using only Josephson logic gates without using semiconductor logic gates.

The interface circuit 10 includes an inverter 1
The output terminal of 1 is connected to the input terminal of the non-inverting gate 12, the output terminal of the non-inverting gate 12 is connected to one input terminal of the 2-input AND gate 13, and the inverter is connected to the other input terminal of the 2-input AND gate 13. 11 input terminals are connected, and the output terminal of the 2-input AND gate 13 is connected to one input terminal of the 2-input AND gate 14.

A clock CK having a duty ratio of 50%, for example, is supplied from the semiconductor circuit to the input terminal of the inverter 11, and data SD is supplied from the semiconductor circuit to the other input terminal of the 2-input AND gate 14. The data SD is a non-return-zero signal that does not return to “0” in synchronization with the falling of the clock CK. Further, the data JD1 extracted from the output terminals of the two-input AND gates 14 and 13 and the width adjustment clock JCK1 representing the timing of reading this data are supplied to the Josephson circuit. Inverter 11, non-inverting gate 12 and 2-input AND gate 1
3 (1A) and (2A) are respectively connected to the power input terminals of FIG.
And three-phase offset AC bias currents φ1, φ2, and φ3 as shown in (3A). The phase difference between the offset AC bias currents φ1 and φ2 and the phase difference between the offset AC bias currents φ2 and φ3 are both 120 °. 2-input AND gate 14
AC bias current φ3 with offset at the power input terminal of
Or φ1 is supplied. The AC bias currents with offsets φ1, φ2, and φ3 are also used in the Josephson circuit.

FIG. 2 shows a specific configuration example of the circuit shown in FIG. The interface circuit 10 includes a non-inverting gate 12
Josephson junctions J1 to J3, inductance L1,
MVTL (Modified V) consisting of L2 and resistors R1 to R3
variable threshold logic) gate, and the inverter 11 is composed of a circuit in which resistors R4 and R5 and a Josephson junction J4 are added to the MVTL gate, and the 2-input AND gate 13 is provided between the two MVTL gates with the resistors R6, R7 and Joseph. The circuit is formed by adding a Son junction J5, and the 2-input AND gate 14 has the same structure as the 2-input AND gate 13. These inverter 11 and non-inverting gate 1
Each of the 2- and 2-input AND gates 13 and 14 is a known Josephson logic gate (Japanese Patent Application No. 58-6364).
No. 8).

When the AC bias current with offset increases and reaches 34% of the peak value, the inverter enters the operating state and holds the output that is the input value inverted at this time, and this output affects the fluctuation of the input value thereafter. However, when the AC bias current with offset decreases and becomes about 20% or less, the output is reset in the non-operating state (power-off state).
In FIG. 3, the Josephson logic gates other than the inverter become in the operating state when the AC bias current with offset increases and exceeds 50% of the peak value, and can respond to the input value. When the AC bias current with offset is reduced and is reduced to about 20% or less, it becomes inoperative and the output is reset. In FIG.
(1B), (2B) and (3B) are operating states of the Josephson logic gates driven by offset AC bias currents φ1, φ2 and φ3 (high level in the figure).
And a non-operating state (low level in the figure). Moreover, the diagonal lines represent the overlapping portions of the operating states, and in this portion, signals are transmitted between the cascade-connected Josephson logic gates.

Next, the operation of the interface circuit 10 configured as described above will be described. In FIG. 3, the time is divided into t1 to t6.

(T1) First, the clock CK is "0",
It is assumed that the outputs of the inverter 11 and the non-inverting gate 12 are both "1", and the outputs of the two-input AND gates 13 and 14 are both "0". In this state, inverter 1
The input value of 1 and the output value of the inverter 11, the non-inverting gate 12, and the 2-input AND gates 13 and 14 are represented by '01100' arranged in this order (the same applies hereinafter).

(T2) Next, when the clock CK rises while the inverter 11 is inactive and the 2-input AND gate 13 is active, as shown in FIG.
It becomes 111X '. That is, the width adjustment clock JCK1 also rises in response to the rise of the clock CK, and at this time, if the data SD is "1", the data JD1 also rises in response to the clock CK. Here, X is the same as SD.

(T3) Next, when the inverter 11 enters the operating state, its output is inverted and becomes "1011X".

(T4, t5) When the inverter 11 is in the operating state (the state in which the output "0" is held) and the non-inverting gate 12 is next in the operating state, it becomes "10000", and J
K1 falls. After that, the output of the non-inverting gate 12 is "0" while the clock CK is "1", and the width adjustment clock JCK1 is "0" until the next rising of the clock CK.
Will remain.

Therefore, the Josephson circuit receives the data JD1 corresponding to the data SD only once with respect to one clock CK output from the semiconductor circuit, and 1
It is possible to prevent a malfunction due to redundant reading of the data SD for each clock CK.

When the offset AC bias current φ1 is supplied to the power input terminal of the two-input AND gate 14, the data JD1 becomes as shown by the dotted line in FIG. 3 (7).

[Second Embodiment] FIG. 4 shows an interface circuit 10A of the second embodiment. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The interface circuit 10A shown in FIG.
Of the inverter 11 and the non-inverting gate 12 are connected in reverse order, and the power input terminal of the non-inverting gate 12 and the inverter 11 are connected.
AC bias currents φ1 and φ2 with an offset are supplied to the power source input terminals of the respective. The other points are the same as in FIG.

Next, the operation of the interface circuit 10A configured as described above will be described with reference to FIGS. 3 (1) to 3 (4). In FIG. 4, the 2-input AND gate 1
The output of 3 is JCK2 and the output of the 2-input AND gate 14 is JD2. Further, it is assumed that an AC bias current φ3 with an offset is supplied to the power input terminal of the 2-input AND gate 14.

(T1) First, the clock CK is "0",
It is assumed that the outputs of the non-inverting gate 12 and the inverter 11 are "0", "1", and the outputs of the two-input AND gates 13 and 14 are "0". This state is represented by '00100' in which the input value of the non-inverting gate 12, the non-inverting gate 12, the inverter 11, and the output values of the two-input AND gates 13 and 14 are arranged in this order (the same applies hereinafter).

(T2) Next, for example, when the clock CK rises when the non-inverting gate 12 is in the non-operating state and the 2-input AND gate 13 is in the operating state, the state becomes “1011X”. That is, the width adjustment clock JCK2 also rises in response to the rise of the clock CK, and at this time, the data S
If D is "1", the data JD2 also rises in response to the clock CK.

(T3) Next, when the non-inverting gate 12 is activated, the state becomes "1111X".

(T4, t5) When the non-inverting gate 12 is in the operating state (holding the output "1") and the inverter 11 is in the operating state next, it becomes "11000" and the width adjustment clock JCK2 rises. Go down. Then clock C
While K is "1", the output of the inverter 11 is "0", and the width adjustment clock JCK2 remains "0" until the next rising of the clock CK.

Therefore, the Josephson circuit receives the data JD2 corresponding to the data SD only once with respect to one clock CK output from the semiconductor circuit, and 1
It is possible to prevent a malfunction due to redundant reading of the data SD for each clock CK. This effect can be obtained even when the AC bias current with offset φ1 is supplied to the power input terminal of the 2-input AND gate 14.

[Third Embodiment] FIG. 5 shows an interface circuit 10B of a third embodiment. The same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

The interface circuit 10B shown in FIG.
A non-inverting gate 12A and a non-inverting gate 12B connected in cascade are used instead of the non-inverting gate 12 of FIG. 1, and AC bias currents with offsets φ1, φ2 and Supplying φ3. The other points are the same as in FIG.

Next, the operation of the interface circuit 10B configured as described above will be described with reference to FIGS. 3 (1) to 3 (4). In FIG. 5, two-input AND gate 1
The output of 3 is JCK3, and the output of the 2-input AND gate 14 is JD3. Further, it is assumed that an AC bias current φ3 with an offset is supplied to the power input terminal of the 2-input AND gate 14.

(T1) First, the clock CK is "0",
It is assumed that the outputs of the non-inverting gates 12A and 12B and the inverter 11 are "0", "0", "1", and the outputs of the two-input AND gates 13 and 14 are "0". In this state, the input values of the non-inverting gate 12A, the non-inverting gates 12A and 12B, the inverter 11, and the output values of the two-input AND gates 13 and 14 are arranged in this order.
Represented by 100 '(same below).

(T2) Next, for example, the non-inverting gate 12A
When the clock CK rises while the 2-input AND gate 13 is in the operating state and the 2-input AND gate 13 is in the operating state, the state '10011
X '. That is, the width adjustment clock JCK3 also rises in response to the rise of the clock CK, and at this time, if the data SD is "1", the data JD3 is also the clock CK.
Get up according to.

(T3) Next, when the non-inverting gate 12A is activated, the state becomes "11011X".

(T4) When the non-inverting gate 12A is in the operating state (state in which "1" is output), the non-inverting gate 1
When 2B is in the operating state, it becomes '11111X'.

(T5) When the non-inverting gate 12B is in the operating state and then the inverter 11 is in the operating state, '111
It becomes 000 'and JK3 falls. After that, the output of the inverter 11 is "0" while the clock CK is "1", and the width adjustment clock JCK3 remains "0" until the next rising of the clock CK.

Therefore, the Josephson circuit receives the data JD3 corresponding to the data SD only once with respect to one clock CK output from the semiconductor circuit, and 1
It is possible to prevent a malfunction due to redundant reading of the data SD for each clock CK. This effect can be obtained even when the AC bias current with offset φ1 is supplied to the power input terminal of the 2-input AND gate 14.

[Fourth Embodiment] FIG. 6 shows an interface circuit 10C of a fourth embodiment. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The interface circuit 10C shown in FIG.
The 2-input AND gate 14 is omitted, and the data SD from the semiconductor circuit is supplied to the other input terminal of the 2-input AND gate 13, and the configuration is simpler than in the first to third embodiments. Unlike the first to third embodiments, the data SD
Must be a signal that returns to zero in synchronization with the clock CK, that is, the data SD must fall in synchronization with the fall of the clock CK when it is at a high level. The other points are the same as in FIG.

Next, the operation of the interface circuit 10C configured as described above will be described with reference to FIGS. 3 (1) to 3 (B). In FIG. 6, the output of the non-inverting gate 12 is JCK4 and the output of the 2-input AND gate 13 is JD4.

(T1) First, data SD and clock C
Both K are “0”, the inverter 11 and the non-inverting gate 1
It is assumed that the outputs of 2 are both "1". This state is represented by '0110' in which the input value of the inverter 11, the output value of the inverter 11, the non-inverting gate 12 and the output value of the AND gate 13 are arranged in this order (the same applies hereinafter).

(T2) Next, when the inverter 11 is in the non-operating state and the non-inverting gate 12 is in the operating state, the clock CK is generated.
Is started, the state becomes “111X”.

(T3) Next, the inverter 11 is in the operating state,
When the non-inverting gate 12 is in the non-operating state, it is' 101X
Becomes

(T4) When the inverter 11 is in the operating state, the non-inverting gate 12 is in the operating state, and the AND gate 13 is in the non-operating state, the state becomes "100X".

(T5) When the non-inverting gate 12 is in the operating state,
Next, when the AND gate 13 becomes the operating state, the state becomes "1".
After that, the width adjustment clock JCK4 falls. After that, when the clock CK falls, the data SD
Also falls at the same time, so the state becomes “0110”.

Therefore, the Josephson circuit receives the data JD4 corresponding to the data SD only once for each clock CK output from the semiconductor circuit, and outputs 1
It is possible to prevent a malfunction due to redundant reading of the data SD for each clock CK.

[Fifth Embodiment] FIG. 7 shows an interface circuit 10D of the fifth embodiment. The same components as those in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted.

In this interface circuit 10D, as shown in FIG.
Inverter 11 and non-inverting gate 12 are connected in reverse order,
Offset bias AC bias currents φ1 and φ2 are supplied to the power input terminals of the non-inverting gate 12 and the inverter 11, respectively. The other points are the same as in FIG.

Next, the operation of the interface circuit 10D configured as described above will be described with reference to FIGS. 3 (1) to 3 (B). In FIG. 7, the output of the inverter 11 is JCK5 and the output of the 2-input AND gate 13 is JCK5.
D5.

(T1) First, data SD and clock C
Both K are '0', the non-inverting gate 12 and the inverter 1
It is assumed that the outputs of 1 are "0" and "1", respectively. This state is represented by '0010' in which the input value of the non-inverting gate 12, the output value of the non-inverting gate 12, the inverter 11 and the AND gate 13 are arranged in this order (the same applies hereinafter).

(T2) Next, when the non-inverting gate 12 is in the non-operating state and the inverter 11 is in the operating state, the clock CK
Is started, the state becomes “101X”.

(T3) Next, when the non-inverting gate 12 is activated, it becomes "111X".

(T4) When the non-inverting gate 12 is in the operating state,
Next, when the inverter 11 becomes operational, '110X'
Becomes

(T5) When the inverter 11 is in the operating state and then the AND gate 13 is in the operating state, the state becomes "11".
Then, the width adjustment clock JCK4 falls. After that, when the clock CK falls, the data SD also falls at the same time, and the state becomes “0010”.

Therefore, the Josephson circuit receives the data JD5 corresponding to the data SD only once for one clock CK output from the semiconductor circuit, and outputs 1
It is possible to prevent a malfunction due to redundant reading of the data SD for each clock CK.

[Sixth Embodiment] FIG. 8 shows an interface circuit 10E of the sixth embodiment. The same components as those in FIG. 7 are designated by the same reference numerals and the description thereof will be omitted.

The interface circuit 10E shown in FIG.
A non-inverting gate 12A and a non-inverting gate 12B connected in cascade are used instead of the non-inverting gate 12 of FIG. 1, and AC bias currents with offsets φ1, φ2 and Supplying φ3. The other points are the same as in FIG. 7.

Next, the operation of the interface circuit 10E configured as described above will be described with reference to FIGS. 3 (1) to 3 (B). In FIG. 8, the output of the inverter 11 is JCK6 and the output of the 2-input AND gate 13 is JCK6.
D6.

(T1) First, data SD and clock C
Both K are "0", and the outputs of the non-inverting gates 12A and 12B and the inverter 11 are "0", "0", and "1", respectively.
It has become. In this state, the non-inversion gate 12A
Input value, non-inverting gates 12A, 12B, inverter 1
1 and the output value of the AND gate 13 are arranged in this order.
Represented by 0010 '(same below).

(T2) Next, when the clock CK rises while the non-inverting gate 12A is in the non-operating state and the non-inverting gate 12B is in the operating state, the state becomes "1001X".

(T3) Next, when the non-inverting gate 12A is activated, it becomes "1101X".

(T4) When the non-inverting gate 12A is in operation and the non-inverting gate 12B is next in operation, "1"
It becomes 111X '.

(T5) When the non-inverting gate 12B is in the operating state and the inverter 11 is in the operating state next time, '111
00 ', and the width adjustment clock JCK6 falls.
After that, when the clock CK falls, the data SD also falls at the same time, and the state becomes '00010'.

Therefore, the Josephson circuit receives the data JD6 corresponding to the data SD only once with respect to one clock CK output from the semiconductor circuit, and 1
It is possible to prevent a malfunction due to redundant reading of the data SD for each clock CK.

In each of the above-mentioned embodiments, the Josephson logic gates 11 to 14 may have a configuration other than the MVTL gate.

[0084]

As described above, since all the interface circuits according to the first to fourth inventions are composed of only Josephson logic gates without using semiconductor logic gates, the high speed performance of the Josephson device is improved. Without harm,
Further, it has an excellent effect that the signal can be accurately transmitted from the semiconductor circuit to the Josephson circuit with a simple configuration without using a special control device or performing special processing on the signal. ..

[Brief description of drawings]

FIG. 1 is an interface circuit diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration example of the circuit of FIG.

FIG. 3 is a timing chart showing the operation of the circuit of FIG.

FIG. 4 is an interface circuit diagram of a second embodiment of the present invention.

FIG. 5 is an interface circuit diagram of a third embodiment of the present invention.

FIG. 6 is an interface circuit diagram of a fourth embodiment of the present invention.

FIG. 7 is an interface circuit diagram of a fifth embodiment of the present invention.

FIG. 8 is an interface circuit diagram of a sixth embodiment of the present invention.

[Explanation of symbols]

 10, 10A to 10E Interface circuit 11 Inverter 12, 12A, 12B Non-inverting gate 13, 14 2 Input AND gate CK clock SD, JD1 to JD6 data JCK1 to JCK6 Width adjustment clock φ1 to φ3 AC bias current with offset J1 to J5 Joseph Son junction L1, L2 Inductance R1 to R7 Resistance

Claims (4)

[Claims] 1. In an interface circuit for transmitting a signal from a semiconductor circuit using a semiconductor element to a Josephson circuit using a Josephson junction element, an output terminal of a first gate (11) is an input terminal of a second gate (12). The second gate is connected to one end of the first AND gate (13), and the first gate (11) is connected to the other input end of the first AND gate (13).
Of the first AND gate (13) is connected to one input end of the second AND gate (14), the first gate (11), the second gate (12) , The first
AND gate (13) and the second AND gate (14)
Is a Josephson logic gate, one of the first gate (11) and the second gate (12) is an inverter and the other is a non-inverting gate, and the first gate (11) and the second gate ( 12) and the power supply input terminals of the first AND gate (13) are supplied with three-phase offset AC bias currents φ1, φ2, and φ3, respectively, and the phase difference between the φ1 and φ2 and the position of the φ2 and φ3. The phase difference is both 120 °, and the second AND gate (1
4) AC bias current φ with offset at the power input terminal
1 or φ3 is supplied, the clock CK is supplied from the semiconductor circuit to the input end of the first gate (11), and the data SD is supplied from the semiconductor circuit to the other input end of the second AND gate (14). Was
The first and gate (13) and the second and gate (1
The output of 4) is supplied to the Josephson circuit as a clock JCK for reading the data JD and the data JD, respectively. 2. In an interface circuit for transmitting a signal from a semiconductor circuit using a semiconductor element to a Josephson circuit using a Josephson junction element, the output end of the first gate (12A) is the second gate (12B).
Connected to the input end of the second gate (12B), the output end of the second gate (12B) is connected to the input end of the third gate (11), and the output end of the third gate (11) is connected to the first AND gate (13). One input terminal is connected, the other input terminal of the first AND gate (13) is connected to the input terminal of the first gate (12A), and the output terminal of the first AND gate (13) is connected to the second input terminal. The first gate (12A), the second gate (12B), the third gate (11), the first AND gate (13) and the second gate are connected to one input terminal of an AND gate (14). The AND gate (14) is composed of a Josephson logic gate, and one of the first gate (12A), the second gate (12B) and the third gate (11) is an inverter and the other two are non-inverting gates. Yes, the first gate (12A), the second gate (1 B), said third gate (11) and the first AND gate (13) of the power input terminal respectively 3-phase offset with alternating bias current to .phi.1, .phi.2, .phi.3 and .phi.3 are supplied, the .phi.1 and φ
2 and the phase difference between φ2 and φ3 are both 120
The AC bias current φ1 or φ3 with offset is supplied to the power source input terminal of the second AND gate (14), and the clock CK is supplied from the semiconductor circuit to the input terminal of the first gate (12A). , The data SD is supplied from the semiconductor circuit to the other input terminal of the second AND gate (14), and the outputs of the first and gate (13) and the second AND gate (14) read the data JD, respectively. An interface circuit which is supplied to the Josephson circuit as the clock JCK and the data JD. 3. In an interface circuit for transmitting a signal from a semiconductor circuit using a semiconductor element to a Josephson circuit using a Josephson junction element, the output terminal of the first gate (11) is the input terminal of the second gate (12). And an output end of the second gate (12) is connected to one input end of the AND gate (13), the first gate (11), the second gate (12) and the AND gate (13). 13) is a Josephson logic gate, one of the first gate (11) and the second gate (12) is an inverter and the other is a non-inverting gate, and the first gate (11) and the second gate (12) Three-phase offset AC bias currents φ1, φ2, and φ3 are supplied to the power supply input terminals of the gate (12) and the AND gate (13), respectively, and the phase difference between the φ1 and φ2 and the phase between the φ2 and φ3 are supplied. Are both 120 °, the clock CK is supplied from the semiconductor circuit to the input end of the first gate (11), and the data SD is supplied from the semiconductor circuit to the other input end of the AND gate (13), A clock J for reading the data JD by the output of the second gate (12) and the output of the AND gate (13), respectively.
An interface circuit characterized by being supplied to the Josephson circuit as CK and the data JD. 4. In an interface circuit for transmitting a signal from a semiconductor circuit using a semiconductor element to a Josephson circuit using a Josephson junction element, the output end of the first gate (12A) is the second gate (12B).
Of the AND gate, the output end of the second gate (12B) is connected to the input end of the third gate (11), and the output end of the third gate (11) is connected to one of the AND gates (13). The first gate (12A), the second gate (12B), the third gate (11) and the AND gate (13) are connected to an input terminal and are configured by a Josephson logic gate. 12
A), the second gate (12B) and the third gate (1
1) one is an inverter and the other two are non-inverting gates, and the power input of the first gate (12A), the second gate (12B), the third gate (11) and the AND gate (13) The three-phase offset AC bias currents φ1, φ2, φ3, and φ3 are supplied to the ends, and the phase difference between φ1 and φ2 and the phase difference between φ2 and φ3 are both 120 °, and the first gate The clock CK is supplied from the semiconductor circuit to the input terminal of (12A), the data SD is supplied from the semiconductor circuit to the other input terminal of the AND gate (13), and the third gate and the AND gate (13). Is supplied to the Josephson circuit as a clock JCK for reading the data JD and the data JD.