JPS5510688A - Control circuit - Google Patents

Control circuit

Info

Publication number
JPS5510688A
JPS5510688A JP8423578A JP8423578A JPS5510688A JP S5510688 A JPS5510688 A JP S5510688A JP 8423578 A JP8423578 A JP 8423578A JP 8423578 A JP8423578 A JP 8423578A JP S5510688 A JPS5510688 A JP S5510688A
Authority
JP
Japan
Prior art keywords
control circuit
multiplied
expression
sum
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8423578A
Other languages
Japanese (ja)
Inventor
Masahiro Yasue
Hideaki Omiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Technical Research and Development Institute of Japan Defence Agency
Original Assignee
Mitsubishi Heavy Industries Ltd
Technical Research and Development Institute of Japan Defence Agency
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd, Technical Research and Development Institute of Japan Defence Agency filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP8423578A priority Critical patent/JPS5510688A/en
Publication of JPS5510688A publication Critical patent/JPS5510688A/en
Pending legal-status Critical Current

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  • Feedback Control In General (AREA)

Abstract

PURPOSE: To obtain a control circuit which is provided with not less than two compensator circuits with a common denominator term to the same input and has the common denominator term made in common.
CONSTITUTION: Output 8 is the sum of outputs 5, 6 and 7 multiplied by (a1), (b1) and (c1) respectively, as shown by expression [I]. Similarly, output 9 is the sum of outputs 5, 6 and 7 multiplied by (a2), (b2) and (c2), as shown by expression [II]. Therefore, the purpose can be attained by two integrators 2 and 3.
COPYRIGHT: (C)1980,JPO&Japio
JP8423578A 1978-07-11 1978-07-11 Control circuit Pending JPS5510688A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8423578A JPS5510688A (en) 1978-07-11 1978-07-11 Control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8423578A JPS5510688A (en) 1978-07-11 1978-07-11 Control circuit

Publications (1)

Publication Number Publication Date
JPS5510688A true JPS5510688A (en) 1980-01-25

Family

ID=13824800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8423578A Pending JPS5510688A (en) 1978-07-11 1978-07-11 Control circuit

Country Status (1)

Country Link
JP (1) JPS5510688A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61500193A (en) * 1983-10-20 1986-01-30 メモレックス・コ−ポレ−ション Track following servo for high density disk files
US4626754A (en) * 1984-03-26 1986-12-02 Societe Europeenne De Propulsion Method and device for reducing the vibrations of rotating machines equipped with an active magnetic suspension

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61500193A (en) * 1983-10-20 1986-01-30 メモレックス・コ−ポレ−ション Track following servo for high density disk files
US4626754A (en) * 1984-03-26 1986-12-02 Societe Europeenne De Propulsion Method and device for reducing the vibrations of rotating machines equipped with an active magnetic suspension

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