JPS5441655A - Frequency divider for high frequency - Google Patents

Frequency divider for high frequency

Info

Publication number
JPS5441655A
JPS5441655A JP10904077A JP10904077A JPS5441655A JP S5441655 A JPS5441655 A JP S5441655A JP 10904077 A JP10904077 A JP 10904077A JP 10904077 A JP10904077 A JP 10904077A JP S5441655 A JPS5441655 A JP S5441655A
Authority
JP
Japan
Prior art keywords
frequency
delay
divider
high frequency
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10904077A
Other languages
Japanese (ja)
Inventor
Tsutomu Ogishi
Toru Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10904077A priority Critical patent/JPS5441655A/en
Publication of JPS5441655A publication Critical patent/JPS5441655A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
    • H03K23/425—Out-of-phase gating or clocking signals applied to counter stages using bistables

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To perform simple circuit constitution, by taking the signal delay from the second to the first clock signal within the delay by gate one stage's share and by taking the signal delay from the first to the second clock signal within the delay by gete two stage's share.
JP10904077A 1977-09-09 1977-09-09 Frequency divider for high frequency Pending JPS5441655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10904077A JPS5441655A (en) 1977-09-09 1977-09-09 Frequency divider for high frequency

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10904077A JPS5441655A (en) 1977-09-09 1977-09-09 Frequency divider for high frequency

Publications (1)

Publication Number Publication Date
JPS5441655A true JPS5441655A (en) 1979-04-03

Family

ID=14500072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10904077A Pending JPS5441655A (en) 1977-09-09 1977-09-09 Frequency divider for high frequency

Country Status (1)

Country Link
JP (1) JPS5441655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344931U (en) * 1989-09-06 1991-04-25

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344931U (en) * 1989-09-06 1991-04-25

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