JPS56120223A - Timing forming circuit - Google Patents
Timing forming circuitInfo
- Publication number
- JPS56120223A JPS56120223A JP2269880A JP2269880A JPS56120223A JP S56120223 A JPS56120223 A JP S56120223A JP 2269880 A JP2269880 A JP 2269880A JP 2269880 A JP2269880 A JP 2269880A JP S56120223 A JPS56120223 A JP S56120223A
- Authority
- JP
- Japan
- Prior art keywords
- delay type
- type flip
- flops
- flop
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To form the timing signal having an arbitrary resolution not limited with the operating speed of a storage circuit, by providing a plurality of delay type flip- flops and obtaining the timing signal through the forming of combined logic value of this output. CONSTITUTION:A plurality of delay type flip-flops 31, 32 are provided in addition to a counter circuit 11 and a storage circuit 12. The counter circuit 11 is operated in the clock C0 having double period of the basic clock. Further, the output of the storage circuit 12 is given to the delay type flip-flop 31 and the output of the delay type flip-flop 31 is given to the delay type flip-flop 32. On the other hand, the operating clocks C1 and C2 given to the flip-flops 31, 32 have double period of the basic clock and different from the phase by one period of the basic clock C. Further, the output of the delay type flop-flops 31, 32, 41, 42 is the timing signals T1, T2, T3, T4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2269880A JPS56120223A (en) | 1980-02-27 | 1980-02-27 | Timing forming circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2269880A JPS56120223A (en) | 1980-02-27 | 1980-02-27 | Timing forming circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56120223A true JPS56120223A (en) | 1981-09-21 |
JPS6213849B2 JPS6213849B2 (en) | 1987-03-30 |
Family
ID=12090084
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2269880A Granted JPS56120223A (en) | 1980-02-27 | 1980-02-27 | Timing forming circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56120223A (en) |
-
1980
- 1980-02-27 JP JP2269880A patent/JPS56120223A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6213849B2 (en) | 1987-03-30 |
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