JPS6213849B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a timing generation circuit.

Conventionally, as a timing generation circuit, a circuit consisting of a counting circuit 1, a memory circuit 2, and a delay type flip-flop 3 has been used, as shown in FIG. Second
The figure is a time chart explaining the circuit of FIG. 1.

This circuit operates a counting circuit 1 using a basic clock C, accesses its output Ai (multiple bits of A0, A1, etc.) as an address input to a memory circuit 2, and reads out information B. After the address is determined, the information is determined after the access time (ta) of the memory circuit 2. In FIG. 2, B0, B1, B2, . . . indicate definitive regions, and b0, b1, b2, . . . indicate uncertain regions.

The output of the memory circuit 2 is applied to a delay type flip-flop 3 which operates with a basic clock or an operation clock having the same period as the basic clock, and a timing signal T is obtained from the delay type flip-flop 3.

The advantage of this circuit is that the timing signal can be easily changed by simply changing the information in the memory circuit.
Furthermore, read-only memory (ROM) is normally used in the storage circuit.
However, since ROM usually has multiple outputs, it has the advantage that a large number of mutually synchronized timing signals can be created with a single set of simple circuits by simply providing delay flip-flops with the same number of outputs. However, as shown in FIG. 2, the conventional circuit has a drawback in that the time (access time) ta until the ROM output is determined is finite, which limits the resolution of the phase pulse width of the timing signal. For example normal ROM
Since ta is about 70 ^ns , it is not possible to create a timing signal with a resolution of 70 ^ns or less.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a circuit for generating a timing signal having an arbitrary resolution that is not limited by the operating speed of a storage circuit.

Accordingly, the present invention achieves the above object by providing a plurality of delay type flip-flops and creating a timing signal by creating a combination of logical values of the outputs thereof.

FIG. 3 shows an embodiment of the present invention, and FIG. 4 shows a time chart.

In FIG. 3, in addition to the counting circuit 11 and the memory circuit 12, a plurality (two) of delay flip-flops 31 and 32 are provided. Since two delay flip-flops are provided, the counting circuit 11 is operated by an operation clock _C0 having a cycle twice that of the basic clock C. The output of the memory circuit 12 is applied to a delay type flip-flop 31, and the output of the delay type flip-flop 31 is applied to a delay type flip-flop 32. Each flip-flop operates on operating clocks C ₁ and C ₂ respectively, but operating clocks C ₁ and C ₂ are based on the basic clock C
This clock has a period twice that of the basic clock C and a phase different from that of the basic clock C by one period length.

The output of the delay type flip-flop 31 is the timing signal T ₁ , the output of the delay type flip-flop 32 is the timing signal T ₂ , the output of the AND circuit 41 that takes the AND of the re-output is the timing signal T ₃ , and the logic that takes the OR of the re-output The output of the sum circuit 42 becomes the timing signal _T4 .

The effects of the present invention become clear when comparing FIGS. 2 and 4. In the conventional example, it was not possible to create a timing signal with a resolution smaller than the access time ta of the memory circuit, but in the embodiment of the present invention, a timing signal with a resolution up to 1/2 of ta can be created. You can. It is clear that even smaller resolutions can be obtained by increasing the number of circuits.

As described above, according to the present invention, a timing generation circuit with several times the performance of the conventional example can be realized by using only the conventional number of expensive memory circuits and adding delay type flip-flops and combinational logic circuits. .

Note that in the above example, the delay type flip-flop is
However, more delay type flip-flops can be provided to increase the resolution. For example, when four delay flip-flops are provided, the counting circuit is operated with an operation clock that has a period four times that of the basic clock, and each of the four flip-flops has a period four times that of the basic clock, and the phase difference between them is equal to the basic clock. It is operated with an operating clock having one cycle length.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a conventional example, Fig. 2 is a time chart explaining Fig. 1, Fig. 3 is a diagram showing an embodiment of the present invention, and Fig. 4 is a time chart explaining Fig. 3. be. 11... Counting circuit, 12... Memory circuit, 31 and 32... Delay type flip-flop, 41...
AND circuit, 42...OR circuit.

Claims (1)

[Scope of Claims] 1. A counting circuit that operates with an operating clock, a memory circuit that is accessed using the output of the counting circuit as an address, and a plurality of delay flip-flops that operate with operating clocks with different phases, comprising: 1
a plurality of delay-type flip-flops in which the output of the memory circuit is inputted to one delay-type flip-flop, and the output of the one delay-type flip-flop is inputted to another delay-type flip-flop; and a combination of logical values of the outputs of the plurality of delay-type flip-flops. A timing creation circuit comprising: a circuit for creating a timing generator; 2. N delay-type flip-flops are provided, the operating clock has a period N times that of the basic clock, and the N operating clocks for operating each of the N delay-type flip-flops have a period N times that of the basic clock. 2. The timing generation circuit according to claim 1, wherein the phase difference between the two clocks is equal to one cycle length of the basic clock.