KR840005634A - Clock regeneration circuit - Google Patents

Clock regeneration circuit Download PDF

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Publication number
KR840005634A
KR840005634A KR1019830002755A KR830002755A KR840005634A KR 840005634 A KR840005634 A KR 840005634A KR 1019830002755 A KR1019830002755 A KR 1019830002755A KR 830002755 A KR830002755 A KR 830002755A KR 840005634 A KR840005634 A KR 840005634A
Authority
KR
South Korea
Prior art keywords
pulse
exclusive logic
contents
memory
regeneration circuit
Prior art date
Application number
KR1019830002755A
Other languages
Korean (ko)
Other versions
KR860001258B1 (en
Inventor
후미히꼬 오꾜가와 (외 1)
Original Assignee
마쓰모도 세이야
파이오니아 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 마쓰모도 세이야, 파이오니아 가부시끼가이샤 filed Critical 마쓰모도 세이야
Publication of KR840005634A publication Critical patent/KR840005634A/en
Application granted granted Critical
Publication of KR860001258B1 publication Critical patent/KR860001258B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

내용 없음No content

Description

클럭 재생회로Clock regeneration circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 한가지 실시예를 보여주는 회로 블럭도.2 is a circuit block diagram showing one embodiment of the present invention.

Claims (1)

펄스발생수단과, 상기 펄스발생수단으로 부터 출력된 펄스에 동기시켜서 입력신호를 일시기억하는 제1 기억수단과, 상기 펄스에 동기시켜 상기 제1 기억수단의 기억내용을 일시기억하는 제2기억수단과, 상기 입력신호 및 상기 제1기억수단의 기억내용에 응한 신호의 배타적 논리화를 취하는 제1배타적 논리화수단과, 상기 제1 및 제2 기억수단의 각각의 기억내용을 각각 나타내는 2신호의 배타적논리화를 취하는 제2 배타적 논리화수단과를 포함하며, 상기 제1 및 제2 배타적 논리화수단의 각 출력의 펄스폭이 서로 같게 되도록 상기 펄스의 반복주파수를 제어하는 것에 의해서 상기 입력신호와 상기 펄스간의 위상차를 없애면서 상기 펄스를 재생클럭으로 출력하는 것을 특징으로하는 클럭재생회로.Pulse generating means, first storage means for temporarily storing an input signal in synchronization with a pulse output from the pulse generating means, and second storage means for temporarily storing the contents of the first memory means in synchronization with the pulse. And a first exclusive logic means for taking exclusive logic of the signal corresponding to the input signal and the contents of the memory of the first memory means, and two signals respectively representing the contents of each of the first and second memory means. And a second exclusive logic means for taking exclusive logic, and controlling the repetition frequency of the pulses so that the pulse widths of the respective outputs of the first and second exclusive logic means are equal to each other. And outputting the pulse to the regeneration clock while eliminating the phase difference between the pulses. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019830002755A 1982-07-24 1983-06-20 Clock regenerating circuit KR860001258B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57129139A JPS5919456A (en) 1982-07-24 1982-07-24 Clock regenerating circuit
JP129139 1982-07-24

Publications (2)

Publication Number Publication Date
KR840005634A true KR840005634A (en) 1984-11-14
KR860001258B1 KR860001258B1 (en) 1986-09-01

Family

ID=15002079

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830002755A KR860001258B1 (en) 1982-07-24 1983-06-20 Clock regenerating circuit

Country Status (2)

Country Link
JP (1) JPS5919456A (en)
KR (1) KR860001258B1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6067556U (en) * 1983-10-14 1985-05-14 ヤマハ株式会社 clock regeneration circuit
US4750193A (en) * 1987-04-20 1988-06-07 International Business Machines Corporation Phase-locked data detector
KR920003598B1 (en) * 1988-12-22 1992-05-04 재단법인 한국전자통신 연구소 Frequency and phase detection circuit with the nrz synchronize
KR930000695B1 (en) * 1990-05-11 1993-01-29 재단법인 한국전자통신연구소 Plase detector for synchronizing bit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148412A (en) * 1978-05-15 1979-11-20 Ricoh Co Ltd Reproduction system for timing information

Also Published As

Publication number Publication date
JPS5919456A (en) 1984-01-31
KR860001258B1 (en) 1986-09-01
JPH0328863B2 (en) 1991-04-22

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