KR940003188A - Synchronous Counter Circuit - Google Patents
Synchronous Counter Circuit Download PDFInfo
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- KR940003188A KR940003188A KR1019920013367A KR920013367A KR940003188A KR 940003188 A KR940003188 A KR 940003188A KR 1019920013367 A KR1019920013367 A KR 1019920013367A KR 920013367 A KR920013367 A KR 920013367A KR 940003188 A KR940003188 A KR 940003188A
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Abstract
다수개의 플립플롭들로 이루어지는 카운터 회로에서 클럭 지연으로 인해 야기되는 오류계수 동작을 제거할 수 있는 동기식 카운터 회로를 제공한다. 이를 위하여 먼저 다수개의 플립플롭으로 구성되는 제1카운터는 전단의 플립플롭 출력단을 다음단의 입력단으로 연결되고 마지막단의 플립플롭 반전 출력단을 최전단의 입력 단으로 연결되는 구성을 가지며, 동일 클럭을 수신하여 환상으로 자리바꿈을 수행하며 제1계수 신호를 발생한다.It provides a synchronous counter circuit that can eliminate the error count operation caused by clock delay in a counter circuit consisting of a plurality of flip-flops. To this end, a first counter composed of a plurality of flip-flops has a configuration in which the flip-flop output stage of the front stage is connected to the input stage of the next stage and the flip-flop inverting output stage of the last stage is connected to the input stage of the last stage. It receives and performs the inversion to the ring and generates the first coefficient signal.
그리고 선택신호 발생기는 제1계수신호 및 제2계수신호를 수신하며, 계수 신호들을 디코딩하여 선택 신호들을 발생한다. 그러면 제2카운터는 전단의 출력과 자신의 출력을 궤환 입력하고 마지막단의 출력을 최전단의 입력단으로 연결되는 구성을 가지며 상기 선택신호의 논리에 따라 수신되는 입력 신호를 선택 출력하는 멀티플렉서들과 상기 멀티플렉서들의 출력단에 각각 대응되어 입력단이 연결되는 다수개의 플립플롭들이 상기 클럭에 의해 상태변화가 수행되어 제2계수신호를 발생한다.The selection signal generator receives the first coefficient signal and the second coefficient signal, and decodes the coefficient signals to generate the selection signals. The second counter has a configuration in which the output of the front end and its output are fed back and the output of the last end is connected to the input terminal of the last stage, and the multiplexers for selectively outputting the input signal according to the logic of the selection signal. A plurality of flip-flops having input terminals connected to the output terminals of the multiplexers, respectively, are changed in state by the clock to generate a second coefficient signal.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 카운터 회로도,2 is a counter circuit diagram according to the present invention,
제3도는 제2도의 동작 파형도.3 is an operational waveform diagram of FIG.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920013367A KR940003188A (en) | 1992-07-25 | 1992-07-25 | Synchronous Counter Circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920013367A KR940003188A (en) | 1992-07-25 | 1992-07-25 | Synchronous Counter Circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR940003188A true KR940003188A (en) | 1994-02-21 |
Family
ID=67147462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920013367A KR940003188A (en) | 1992-07-25 | 1992-07-25 | Synchronous Counter Circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940003188A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100302330B1 (en) * | 1999-09-08 | 2001-11-07 | 서평원 | A device of suppling frame pulse of counter |
| KR102506028B1 (en) | 2021-10-27 | 2023-03-07 | 금호타이어 주식회사 | Tire bead storage rack |
-
1992
- 1992-07-25 KR KR1019920013367A patent/KR940003188A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100302330B1 (en) * | 1999-09-08 | 2001-11-07 | 서평원 | A device of suppling frame pulse of counter |
| KR102506028B1 (en) | 2021-10-27 | 2023-03-07 | 금호타이어 주식회사 | Tire bead storage rack |
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|---|---|---|---|
| WITN | Withdrawal due to no request for examination |