KR970004486A - Time slot position signal generator - Google Patents

Time slot position signal generator Download PDF

Info

Publication number
KR970004486A
KR970004486A KR1019950017947A KR19950017947A KR970004486A KR 970004486 A KR970004486 A KR 970004486A KR 1019950017947 A KR1019950017947 A KR 1019950017947A KR 19950017947 A KR19950017947 A KR 19950017947A KR 970004486 A KR970004486 A KR 970004486A
Authority
KR
South Korea
Prior art keywords
signal
time slot
flip
flop
block
Prior art date
Application number
KR1019950017947A
Other languages
Korean (ko)
Other versions
KR0152727B1 (en
Inventor
한상철
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950017947A priority Critical patent/KR0152727B1/en
Publication of KR970004486A publication Critical patent/KR970004486A/en
Application granted granted Critical
Publication of KR0152727B1 publication Critical patent/KR0152727B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

본 발명의 타임 슬롯 위치신호 발생장치는 2M CEPT 프레임 구조를 가지는 데이타 스트림에서 타임 슬롯에서 데이터를 추출하거나 또는 해당 타임 슬롯에 데이타를 삽입할 수 있도록 타임 슬롯의 위치신호를 발생한다.The time slot position signal generator of the present invention generates a time slot position signal to extract data from a time slot or insert data into a corresponding time slot from a data stream having a 2M CEPT frame structure.

본 발명은 32개의 타임 슬롯을 블록으로 분할하여 타임 슬롯 블록신호를 발생하고, 발생한 타임 슬롯 블록신호를 이용하여 타임 슬롯 블록내의 타임슬롯 위치신호를 발생하는 것으로서 2.048㎒의 클럭신호를 카운터가 분주하고, 카운터의 분주신호를 이용하여 타임 슬롯 분할수단이 32개의 타임 슬롯을 4개의 블록으로 분할하여 0, 8, 16 및 24번째 타임 슬롯 위치에서 블록 위치신호를 발생함과 아울러 카운터의 분주신호중에서 각각의 타임 슬롯의 폭을 가지는 1/8 분주신호를 플립플롭이 출력하며, 타임 슬롯 분할수단이 발생한 블록 위치신호에서 선택된 하나의 블록 위치신호에 따라 블록 초기신호 발생수단이 플립플롭의 출력신호로 각각의 타입 슬롯의 폭을 가지는 타임 슬롯 블록의 초기신호를 발생하며, 블록 초기신호 발생수단이 발생한 초기신호를 타임 슬롯 위치신호 발생수단이 플립플롭의 출력신호에 따라 시프트시켜 타임 슬롯 위치신호를 발생한다.The present invention generates a time slot block signal by dividing 32 time slots into blocks, and generates a time slot position signal in a time slot block using the generated time slot block signal. The counter divides a clock signal of 2.048 MHz. By using the divided signal of the counter, the time slot dividing means divides 32 time slots into four blocks to generate a block position signal at the 0, 8, 16, and 24th time slot positions, respectively. The flip-flop outputs a 1/8 divided signal having a width of a time slot of?, And the block initial signal generating means is an output signal of the flip-flop according to one block position signal selected from the block position signal at which the time slot division means is generated. Generates an initial signal of a time slot block having a width of a type slot of The time slot position signal generating means shifts according to the output signal of the flip-flop to generate the time slot position signal.

Description

타임 슬롯 위치신호 발생장치Time slot position signal generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 타임 슬롯 위치신호 발생장치를 보인 회로도, 제2도의 (가)~(거)는 제2도의 각 부의 동작 파형도.FIG. 1 is a circuit diagram showing a time slot position signal generator according to the present invention, and FIG. 2A to FIG. 2 are operational waveform diagrams of the parts shown in FIG.

Claims (5)

반전 클럭신호(/CLK)를 분주하는 카운터(1)(2)와, 상기 카운터(1)(2)의 분주신호에 따라 타임 슬롯을 분할한 타임 슬롯 블록신호(CB1∼CB4)를 발생하는 타임 슬롯 분할수단(3)과, 클럭신호(CLK)에 따라 상기 카운터(1)의 출력신호로 타임 슬롯의 폭을 가지는 펄스신호를 발생하는 플립플롭(4)과, 상기 타임 슬롯 분할수단(3)의 출력신호에서 선택된 하나의 타임 슬롯 블록 신호(CB1) 또는 (CB2∼CB4)에 따라 상기 플립플롭(4)의 출력신호를 출력하는 블록 초기신호 발생수단(5)과, 상기 플립플롭(4)의 출력신호에 따라 상기 블록 초기신호 발생수단(5)의 출력신호를 시프트시켜 전화기 상향신호(FSX1∼FSX3)를 발생함과 아울러 가입자 선택신호 (SUB1)(SUB|2)에 따라 전화기 하향신호(FSR1∼FSR3)를 발생하는 타임 슬롯 위치신호 발생수단(6)으로 구성함을 특징으로 하는 타임 슬롯 위치신호 발생장치.Counter (1) and (2) for dividing the inverted clock signal (/ CLK) and time slot block signals (CB 1 to CB 4 ) in which time slots are divided according to the division signals of the counters (1) and (2). Time slot dividing means 3, a flip-flop 4 for generating a pulse signal having a width of a time slot as an output signal of the counter 1 in accordance with a clock signal CLK, and the time slot dividing means ( 3) the output signal of one time slot signal blocks (CB 1) or (2 CB ~CB 4) blocks the initial signal generating means (5) for outputting an output signal of the flip-flop 4 in accordance with, and selected from the According to the output signal of the flip-flop 4, the output signal of the block initial signal generating means 5 is shifted to generate the telephone up signal FSX 1 to FSX 3 , and the subscriber selection signal SUB 1 (SUB | 2 ) a time slot position signal generating means 6 for generating the downlink signals FSR 1 to FSR 3 according to the present invention. Is a time slot position signal generator. 제1항에 있어서, 타임 슬롯 분할수단(3)은, 카운터(1)(2)의 출력단자(Q13)(Q20,Q21)에서 출력되는 1/16, 1/32 및 1/64 분주신호를 논리 합하는 오아 게이트(31)와, 상기 오아 게이트(31)의 출력신호에 따라 인에이블되면서 상기 카운터(1)에서 출력되는 1/128 및 1/256 분주신호를 디코딩하여, 0, 8, 16 및 24번째 타임 슬롯 블록신호(CB1∼CB4)를 발생하는 디코더(32)로 구성함을 특징으로 하는 타임 슬롯 위치신호 발생장치.The time slot dividing means (3) according to claim 1, wherein the time slot dividing means (3) is 1/16, 1/32 and 1/64 output from the output terminals (Q 13 ) (Q 20 , Q 21 ) of the counter (1) (2). The OR gate 31 for logical sum of the divided signals and the 1/128 and 1/256 divided signals outputted from the counter 1 while being enabled according to the output signal of the OR gate 31 are decoded. And a decoder (32) for generating 16th and 24th time slot block signals (CB 1 to CB 4 ). 제1항에 있어서, 플립플롭(4)은 카운터(1)의 1/8 분주신호를 클럭신호(CLK)에 따라 출력하는 것을 특징으로 하는 타임 슬롯 위치신호 발생장치.2. The apparatus as claimed in claim 1, characterized in that the flip-flop (4) outputs the 1/8 divided signal of the counter (1) according to the clock signal (CLK). 제1항에 있어서, 블록 초기신호 발생수단(5)은, 타임 슬롯 분할수단(3)에서 출력되는 하나의 타임 슬롯 블록신호(CB1) 또는 (CB2∼CB4)를 반전시키는 인버터(51)와, 상기 인버터(51)의 출력신호를 클럭신호로 하여 상기 플립플롭(4)의 출력신호를 출력하는 플립플롭(52)으로 구성함을 특징으로 하는 타임 슬롯 위치신호 발생장치.2. The inverter 51 according to claim 1, wherein the block initial signal generating means (5) inverts one time slot block signal (CB 1 ) or (CB 2 to CB 4 ) output from the time slot dividing means (3). And a flip-flop (52) for outputting the output signal of the flip-flop (4) using the output signal of the inverter (51) as a clock signal. 제1항에 있어서, 타임 슬롯 위치신호 발생수단(6)은, 플립플롭(4)의 출력신호를 반전시키는 인버터(61)와, 블록 초기신호 발생수단(5)의 출력신호를 상기 인버터(61)의 출력신호에 따라 시프트시키고 첫번째, 두번째 및 세번째 시프트 신호를 전화기 상향신호(FSX1∼FSX3)로 출력하는 직렬/병렬 시프트 레지스터(62) 및 플립플롭(63)과, 상기 직렬/병렬 시프트 레지스터(62) 및 플립플롭(63)이 출력하는 첫번째, 네번째, 일곱번째 시프트 신호와, 두번째, 다섯번째 및 여덟번째 시프트 신호와, 세번째, 여섯번째 및 아홉번째 시프틔 신호를 가입자선택신호(SUB1)(SUB2)에 따라 각기 전화기 하향신호(FSR1∼FSR3)로 출력하는 멀티플렉서(64)(65)(66)로 구성함을 특징으로 하는 타임 슬롯 위치신호 발생장치.The time slot position signal generating means (6) comprises: an inverter (61) for inverting the output signal of the flip-flop (4) and an output signal of the block initial signal generating means (5). ) and shifted in accordance with an output signal of the first, the second and third up-shift signal telephone signal (FSX 1 ~FSX 3) into an output serial / parallel shift register 62 and the flip-flop 63 and, the S / P shift to The first, fourth, and seventh shift signals, the second, fifth, and eighth shift signals, and the third, sixth, and ninth shift signals output from the registers 62 and the flip-flop 63 are selected by the subscriber selection signal (SUB). 1 ) A time slot position signal generator, characterized in that it comprises a multiplexer (64) (65) (66) for outputting the downlink signals (FSR 1 to FSR 3 ) of the telephone according to (SUB 2 ), respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017947A 1995-06-28 1995-06-28 Device for generating positioning signal of time slot KR0152727B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950017947A KR0152727B1 (en) 1995-06-28 1995-06-28 Device for generating positioning signal of time slot

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950017947A KR0152727B1 (en) 1995-06-28 1995-06-28 Device for generating positioning signal of time slot

Publications (2)

Publication Number Publication Date
KR970004486A true KR970004486A (en) 1997-01-29
KR0152727B1 KR0152727B1 (en) 1998-11-02

Family

ID=19418618

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950017947A KR0152727B1 (en) 1995-06-28 1995-06-28 Device for generating positioning signal of time slot

Country Status (1)

Country Link
KR (1) KR0152727B1 (en)

Also Published As

Publication number Publication date
KR0152727B1 (en) 1998-11-02

Similar Documents

Publication Publication Date Title
KR960036749A (en) Variable-length decoding device
KR870010688A (en) Noise Pulse Suppression Circuit
KR970004486A (en) Time slot position signal generator
KR960036748A (en) Variable-length decoding device
KR910013751A (en) NRZ / CMI (II) Code Inverter
KR940003188A (en) Synchronous Counter Circuit
KR0186058B1 (en) Synchronous Clock Generation Circuit
KR900702709A (en) Voice signal demodulation circuit
KR970013690A (en) Glitch-independent control signal generator
KR920014182A (en) Synchronous signal detection circuit
KR910002121A (en) Frequency Variable Variable PWM Signal Generation Circuit
KR980006918A (en) 50% Duty Cycle Data Generator (50% Duty Cycle Data Generator)
KR970049379A (en) 16-bit parallel descrambling data generation circuit of 16-bit parallel descrambler
KR970031351A (en) Division Circuit with 50 Percent Duty Output
KR960027343A (en) 7-division circuit
KR920015739A (en) Clock variable circuit
KR970064051A (en) Gap-clock generator
KR970031525A (en) Synchronous Transmission Module Level 1 Frame Parallel Scrambler
KR930022716A (en) Waveform generation circuit
KR940020828A (en) Frequency multiplication circuit
KR950029926A (en) Parallel Multiplier for Binary Complement Generation
KR960027859A (en) Numerically Controlled Phase Shift Clock Generator
KR920020853A (en) Frequency division circuit using ring counter
KR930024337A (en) Frame Synchronization Detection Method and Circuit for Demultiplexing Data Transmission System
KR920014121A (en) Analog Conference Circuit of Switching System

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950628

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19950628

Comment text: Request for Examination of Application

PG1501 Laying open of application
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19980624

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19980630

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19980630

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20010525

Start annual number: 4

End annual number: 4

FPAY Annual fee payment

Payment date: 20020517

Year of fee payment: 5

PR1001 Payment of annual fee

Payment date: 20020517

Start annual number: 5

End annual number: 5

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20040310