KR960027343A

KR960027343A - 7-division circuit

Info

Publication number: KR960027343A
Application number: KR1019940034026A
Authority: KR
Inventors: 이창문; 주범순
Original assignee: 양승택; 재단법인 한국전자통신연구소; 조백제; 한국전기통신공사
Priority date: 1994-12-13
Filing date: 1994-12-13
Publication date: 1996-07-22

Abstract

본 발명은 정확한 50퍼센트의 듀티 사이클(duty cycle)을 갖는 7분주회로에 관한 것으로, 분주될 클럭 펄스(CP)를 클럭 펄스 입력단에 연결하고, 병렬 입력값에 의해 출력단(Q2)에서 주기적으로 7분주신호를 발생하는 카운터(101)와, 상기 분주될 클럭 펄스(CP)의 반전된 클럭 펄스(/CP)를 클럭 펄스로 하여 상기 카운터(101)의 출력단(Q2) 신호를 데이타로 입력받는 D 플립플롭(102)과, 상기 카운터(101)의 출력단(Q2) 신호와 상기 D 플립플롭(102)의 출력단(Q) 신호를 논리합하여 7분주 클럭을 출력하는 AND 게이트(103)를 구비하는 것을 특징으로 하여 튜티 사이클이 정확히 50퍼센트인 출력을 발생하고, 간단하고 상용화된 소자로 구성되어 있어 구현하기가 용이하며, 분주될 반전 클럭 펄스에 의한 지연 회로에 의해 다른 홀수 분주기에도 응용이 가능한 효과가 있다.The present invention relates to a seven-dividing circuit having an accurate 50 percent duty cycle, wherein a clock pulse (CP) to be divided is connected to a clock pulse input stage, and the output stage Q2 is periodically D which receives the output terminal Q2 signal of the counter 101 as data using a counter 101 for generating a divided signal and an inverted clock pulse / CP of the clock pulse CP to be divided as a clock pulse; A flip-flop 102 and an AND gate 103 for outputting a 7-division clock by ORing the output terminal Q2 signal of the counter 101 and the output terminal Q signal of the D flip-flop 102. It features an output with exactly 50 percent duty cycle, and is simple and commercially available, making it easy to implement, and it can be applied to other odd dividers by a delay circuit caused by an inverted clock pulse to be divided. There is.

Description

7-division circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 7분주회로 구성도, 제2도는 제1도의 각부분에 대한 신호 파형도.1 is a block diagram of a seven-division circuit according to the present invention, and FIG. 2 is a signal waveform diagram for each part of FIG.

Claims

A counter 101 which connects a clock pulse CP to be divided to a clock pulse input terminal and generates a seven-division signal periodically at an output terminal Q2 by a parallel input value, and the inverted clock pulse CP to be divided. D flip-flop 102 which receives the output terminal Q2 signal of the counter 101 as data using a clock pulse / CP as a clock pulse, an output terminal Q2 signal of the counter 101 and the D flip And an AND gate (103) for outputting a seventh division clock by ORing the output (Q) signal of the flop (102).

※ Note: The disclosure is based on the initial application.