KR920008770A - Timing Control Circuit of Synchronous Memory Device - Google Patents

Timing Control Circuit of Synchronous Memory Device Download PDF

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Publication number
KR920008770A
KR920008770A KR1019910018087A KR910018087A KR920008770A KR 920008770 A KR920008770 A KR 920008770A KR 1019910018087 A KR1019910018087 A KR 1019910018087A KR 910018087 A KR910018087 A KR 910018087A KR 920008770 A KR920008770 A KR 920008770A
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KR
South Korea
Prior art keywords
circuit
clock
synchronous memory
memory device
output
Prior art date
Application number
KR1019910018087A
Other languages
Korean (ko)
Other versions
KR100229119B1 (en
Inventor
요시노리 사또
마나부 가또
Original Assignee
오오가 노리오
소니 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2276787A external-priority patent/JPH04153994A/en
Priority claimed from JP1990108818U external-priority patent/JPH0466816U/ja
Application filed by 오오가 노리오, 소니 가부시끼가이샤 filed Critical 오오가 노리오
Publication of KR920008770A publication Critical patent/KR920008770A/en
Application granted granted Critical
Publication of KR100229119B1 publication Critical patent/KR100229119B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음No content

Description

동기형 메모리 장치의 타이밍 제어회로Timing Control Circuit of Synchronous Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명의 제1실시예인 클럭 천이 검출 회로를 도시한 도면이다.5 is a diagram showing a clock transition detection circuit as a first embodiment of the present invention.

Claims (3)

듀티가 다른 외부 클럭 펄스가 입력되도, 천이 검출 회로를 통해 동기형 메모리의 어드레스 레지스터, 센스앰프, 출력 레지스터 등 각 블럭에 듀티가 일정한 클럭 펄스를 공급하는 것을 특징으로 하는 동기형 메모리 장치의 타이밍 제어회로.Timing control of a synchronous memory device characterized by supplying a constant clock pulse to each block such as an address register, a sense amplifier, and an output register of the synchronous memory through a transition detection circuit even when an external clock pulse having a different duty is inputted. Circuit. 제1항에 있어서, 피검출 클럭펄스를 1/2분주하는 분주 회로를 설치하고, 이 분주 회로의 출력 펄스의 지연량을 상이하게 한 2개의 펄스를 1개의 논리게이트에 입력해서 이 논리 게이트에서 검출펄스를 얻게하는 것을 특징으로하는 클럭 천이 검출회로.2. A divider circuit for dividing the detected clock pulses by half is provided, and two pulses having different delay amounts of the output pulses of the divided circuits are input to one logic gate, thereby A clock transition detection circuit characterized by obtaining a detection pulse. 클럭 천이 검출회로의 다른쪽 출력 단자로부터 NOR회로의 다른쪽 단자로 클럭 천이 디스에이블 펄스를 송출하도록 연결하며, 출력 노이즈가 발생하는 출력 데이타의 변화시에 있어서 상기 클럭 천이 검출회로를 비활성으로 하는 것을 특징으로 하는 동기형 메모리 장치의 제어 회로.Connect the clock transition disable pulse from the other output terminal of the clock transition detection circuit to the other terminal of the NOR circuit, and disable the clock transition detection circuit in the case of change of output data in which output noise occurs. A control circuit for a synchronous memory device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910018087A 1990-10-16 1991-10-15 Timing control circuit of synchronous type memory apparatus KR100229119B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP90-276787 1990-10-16
JP2276787A JPH04153994A (en) 1990-10-16 1990-10-16 Synchronization memory
JP90-108818 1990-10-17
JP1990108818U JPH0466816U (en) 1990-10-17 1990-10-17

Publications (2)

Publication Number Publication Date
KR920008770A true KR920008770A (en) 1992-05-28
KR100229119B1 KR100229119B1 (en) 1999-11-01

Family

ID=26448626

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910018087A KR100229119B1 (en) 1990-10-16 1991-10-15 Timing control circuit of synchronous type memory apparatus

Country Status (1)

Country Link
KR (1) KR100229119B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100556179B1 (en) * 1998-03-30 2006-03-03 산요덴키가부시키가이샤 Address transition detection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100556179B1 (en) * 1998-03-30 2006-03-03 산요덴키가부시키가이샤 Address transition detection circuit

Also Published As

Publication number Publication date
KR100229119B1 (en) 1999-11-01

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