JPH0466816U - - Google Patents
Info
- Publication number
- JPH0466816U JPH0466816U JP1990108818U JP10881890U JPH0466816U JP H0466816 U JPH0466816 U JP H0466816U JP 1990108818 U JP1990108818 U JP 1990108818U JP 10881890 U JP10881890 U JP 10881890U JP H0466816 U JPH0466816 U JP H0466816U
- Authority
- JP
- Japan
- Prior art keywords
- logic gate
- dividing circuit
- circuit
- frequency dividing
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 230000007704 transition Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案クロツク遷移検出回路の一つの
実施例を示す回路図、第２図は第１図に示すクロ
ツク遷移検出回路の動作を示すタイムチヤート、
第３図はクロツク遷移検出回路が使用される回路
の一例である同期型メモリの回路ブロツク図、第
４図はクロツク遷移検出回路の従来例を示す回路
図、第５図は第４図に示すクロツク遷移検出回路
の動作を示すタイムチヤートである。
符号の説明、１……遅延回路、２ａ……論理ゲ
ート（ＥＸ−ＮＯＲ）、３……分周回路。
FIG. 1 is a circuit diagram showing one embodiment of the clock transition detection circuit of the present invention, and FIG. 2 is a time chart showing the operation of the clock transition detection circuit shown in FIG. 1.
Figure 3 is a circuit block diagram of a synchronous memory which is an example of a circuit in which a clock transition detection circuit is used, Figure 4 is a circuit diagram showing a conventional example of a clock transition detection circuit, and Figure 5 is shown in Figure 4. 3 is a time chart showing the operation of a clock transition detection circuit. Explanation of symbols: 1... Delay circuit, 2a... Logic gate (EX-NOR), 3... Frequency divider circuit.
Claims (1)
を設け、該分周回路の出力パルスの遅延量を異な
らせた２つのパルスを１つの論理ゲートに入力し
て該論理ゲートから検出パルスを得るようにした ことを特徴とするクロツク遷移検出回路。[Claims for Utility Model Registration] A frequency dividing circuit that divides the frequency of the detected clock pulse by 1/2 is provided, and two pulses with different delay amounts of the output pulses of the frequency dividing circuit are input to one logic gate. A clock transition detection circuit characterized in that a detection pulse is obtained from the logic gate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990108818U JPH0466816U (en) | 1990-10-17 | 1990-10-17 | |
| KR1019910018087A KR100229119B1 (en) | 1990-10-16 | 1991-10-15 | Timing control circuit of synchronous type memory apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990108818U JPH0466816U (en) | 1990-10-17 | 1990-10-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0466816U true JPH0466816U (en) | 1992-06-12 |
Family
ID=31855955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990108818U Pending JPH0466816U (en) | 1990-10-16 | 1990-10-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0466816U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0216618B2 (en) * | 1982-06-21 | 1990-04-17 | Yaesu Musen Kk |
-
1990
- 1990-10-17 JP JP1990108818U patent/JPH0466816U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0216618B2 (en) * | 1982-06-21 | 1990-04-17 | Yaesu Musen Kk |