JPS6326129U - - Google Patents
Info
- Publication number
- JPS6326129U JPS6326129U JP12015786U JP12015786U JPS6326129U JP S6326129 U JPS6326129 U JP S6326129U JP 12015786 U JP12015786 U JP 12015786U JP 12015786 U JP12015786 U JP 12015786U JP S6326129 U JPS6326129 U JP S6326129U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- frequency
- signal
- clock means
- synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Dot-Matrix Printers And Others (AREA)
- Laser Beam Printer (AREA)
- Pulse Circuits (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の構成を示すブロツク図、第２
図は従来のＨＳ発生回路を示すブロツク図、第３
図は本考案の一実施例のＨＳ信号発生回路を示す
回路構成図、第４図は第３図の回路における各部
の波形を示す説明図、第５図はレーザープリンタ
ーの説明図である。
符号の説明、１０…クロツク手段、１１…検出
手段、１２…分周手段、１３…カウンタ手段、１
４…ゲート手段。
Figure 1 is a block diagram showing the configuration of the present invention, Figure 2 is a block diagram showing the configuration of the present invention.
The figure is a block diagram showing a conventional HS generation circuit.
4 is an explanatory diagram showing waveforms of various parts in the circuit of FIG. 3, and FIG. 5 is an explanatory diagram of a laser printer. Explanation of symbols: 10... Clock means, 11... Detection means, 12... Frequency division means, 13... Counter means, 1
4...Gate means.
Claims (1)
手段を同期した検出信号を送出する検出手段と、
前記クロツク手段に同期して動作し該検出信号が
あると前記クロツク手段のクロツクパルスを分周
する分周手段と、前記クロツク手段に同期して動
作し該分周手段からの分周信号をカウントするカ
ウンタ手段と、該カウンタ手段からの出力がある
と前記クロツク手段に同期化した信号を出力する
ゲート手段とを備えることを特徴とする同期化遅
延回路。 clock means; detection means for detecting an input signal and sending out a detection signal that synchronizes the clock means;
a frequency dividing means which operates in synchronization with the clock means and divides the frequency of the clock pulse of the clock means when the detection signal is received; and a frequency division means which operates in synchronization with the clock means and counts the frequency divided signal from the frequency division means. A synchronized delay circuit comprising a counter means and a gate means for outputting a synchronized signal to the clock means when there is an output from the counter means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12015786U JPS6326129U (en) | 1986-08-05 | 1986-08-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12015786U JPS6326129U (en) | 1986-08-05 | 1986-08-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6326129U true JPS6326129U (en) | 1988-02-20 |
Family
ID=31008214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12015786U Pending JPS6326129U (en) | 1986-08-05 | 1986-08-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6326129U (en) |
-
1986
- 1986-08-05 JP JP12015786U patent/JPS6326129U/ja active Pending
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