JPS62151249U - - Google Patents
Info
- Publication number
- JPS62151249U JPS62151249U JP3917286U JP3917286U JPS62151249U JP S62151249 U JPS62151249 U JP S62151249U JP 3917286 U JP3917286 U JP 3917286U JP 3917286 U JP3917286 U JP 3917286U JP S62151249 U JPS62151249 U JP S62151249U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- timing signal
- output
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例を示す回路図である
。第２図は第１図における回路中の各点における
信号波形図である。
５……タイミング信号形成回路、６……オア回
路、９……重畳回路、２４……ケーブル、２５…
…ケーブル、３０……第１の比較回路、３１……
第２の比較回路、３５……積分回路、３８……イ
ンバータ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a signal waveform diagram at each point in the circuit in FIG. 1. 5... Timing signal forming circuit, 6... OR circuit, 9... Superimposition circuit, 24... Cable, 25...
...Cable, 30...First comparison circuit, 31...
Second comparison circuit, 35...integrator circuit, 38...inverter.
Claims (1)
のにおいて、送信局にクロツク信号の立ち上がり
と同期して立ち上げたパルス幅の短かいタイミン
グ信号を出力するタイミング信号形成回路と、デ
ータ信号とタイシング信号を入力するオア回路と
、該オア回路の出力信号とタイミング信号とから
３値信号を出力する重畳回路を設け、受信局には
高低異なる基準値に設定した第１、第２の比較回
路と、第１の比較回路の出力を積分する積分回路
と第２の比較回路の出力を入力したインバータを
設けたことを特徴とする二芯式送受信装置。 In a system in which a transmitting station and a receiving station are connected by a two-core cable, there is a timing signal forming circuit that outputs a timing signal with a short pulse width that rises in synchronization with the rising edge of a clock signal to the transmitting station, and a data signal and timing signal. An OR circuit that inputs a signal and a superimposition circuit that outputs a ternary signal from the output signal of the OR circuit and the timing signal are provided, and the receiving station has first and second comparator circuits set to different reference values. A two-core transmitting/receiving device comprising: an integrator circuit that integrates the output of the first comparator circuit; and an inverter that receives the output of the second comparator circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3917286U JPS62151249U (en) | 1986-03-17 | 1986-03-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3917286U JPS62151249U (en) | 1986-03-17 | 1986-03-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62151249U true JPS62151249U (en) | 1987-09-25 |
Family
ID=30852099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3917286U Pending JPS62151249U (en) | 1986-03-17 | 1986-03-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62151249U (en) |
-
1986
- 1986-03-17 JP JP3917286U patent/JPS62151249U/ja active Pending
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