JPS61140638U - - Google Patents
Info
- Publication number
- JPS61140638U JPS61140638U JP2345785U JP2345785U JPS61140638U JP S61140638 U JPS61140638 U JP S61140638U JP 2345785 U JP2345785 U JP 2345785U JP 2345785 U JP2345785 U JP 2345785U JP S61140638 U JPS61140638 U JP S61140638U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- signal
- input
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Description
第1図は本考案のパルス信号出力回路、第2図
は従来のパルス信号出力回路、第3図、第4図は
出力タイムチヤート、第5図は同期化回路ブロツ
ク図、第6図は同期化タイムチヤート。
1:アツプダウンカウンタ、2:出力制御回路
、3:同期化回路。
Figure 1 is a pulse signal output circuit of the present invention, Figure 2 is a conventional pulse signal output circuit, Figures 3 and 4 are output time charts, Figure 5 is a synchronization circuit block diagram, and Figure 6 is a synchronization circuit. ization time chart. 1: up/down counter, 2: output control circuit, 3: synchronization circuit.
Claims (1)
の信号を一定のパルス幅以上のパルス信号に変換
する回路において、入力パルス数と出力したパル
ス数を計数するためのアツプダウンカウンタを使
用し、入力用パルス信号と、パルス出力終了信号
を同期化するための回路を設け、入力パルス信号
相互およびパルス出力終了信号を同期化して、ア
ツプダウンカウンタに入力し、入力パルスの数と
同数の一定パルス幅のパルス信号を出力するよう
にしたパルス信号出力回路。 In a circuit that converts a signal that is the sum of multiple output pulse signals with a short pulse period into a pulse signal with a fixed pulse width or more, an up-down counter is used to count the number of input pulses and the number of output pulses. A circuit is provided to synchronize the input pulse signal and the pulse output end signal, and the input pulse signals and the pulse output end signal are synchronized and input to the up-down counter, and a constant pulse width of the same number as the number of input pulses is provided. A pulse signal output circuit that outputs a pulse signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2345785U JPS61140638U (en) | 1985-02-22 | 1985-02-22 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2345785U JPS61140638U (en) | 1985-02-22 | 1985-02-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61140638U true JPS61140638U (en) | 1986-08-30 |
Family
ID=30516708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2345785U Pending JPS61140638U (en) | 1985-02-22 | 1985-02-22 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61140638U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9273755B2 (en) | 2009-03-27 | 2016-03-01 | Ricardo Uk Limited | Method and apparatus for balancing a flywheel |
US9391489B2 (en) | 2010-11-17 | 2016-07-12 | Ricardo Uk Limited | Magnetic coupler having magnets with different magnetic strengths |
-
1985
- 1985-02-22 JP JP2345785U patent/JPS61140638U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9273755B2 (en) | 2009-03-27 | 2016-03-01 | Ricardo Uk Limited | Method and apparatus for balancing a flywheel |
US9391489B2 (en) | 2010-11-17 | 2016-07-12 | Ricardo Uk Limited | Magnetic coupler having magnets with different magnetic strengths |