JPS63118647U - - Google Patents
Info
- Publication number
- JPS63118647U JPS63118647U JP781887U JP781887U JPS63118647U JP S63118647 U JPS63118647 U JP S63118647U JP 781887 U JP781887 U JP 781887U JP 781887 U JP781887 U JP 781887U JP S63118647 U JPS63118647 U JP S63118647U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- majority
- signal
- synchronization
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims 1
Landscapes
- Hardware Redundancy (AREA)
Description
第１図はこの考案による多数決同期制御回路の
一実施例、第２図は従来の多数決同期制御回路の
例、第３図はこの考案による多数決同期制御回路
の動作タイミングチヤート、第４図は従来の多数
決同期制御回路の動作タイミングチヤートである
。
図において１は外部回路ａ、２は外部回路ｂ、
３は外部回路ｃ、４は多数決回路、９は計数回路
、１１は同期制御信号発生回路、１ａは外部回路
１より出力される同期信号ａ、２ａは外部回路２
より出力される同期信号ｂ、３ａは外部回路３よ
り出力される同期信号ｃ、５は多数決回路４より
出力される同期信号、８は多数決回路４より出力
される多数決エラー信号、１０は計数回路９の出
力信号、７は同期制御信号発生回路１１より出力
される同期制御信号である。なお、各図中同一符
号は同一または相当部分を示す。
Fig. 1 shows an example of the majority synchronous control circuit according to this invention, Fig. 2 shows an example of a conventional majority synchronous control circuit, Fig. 3 shows an operation timing chart of the majority synchronous control circuit according to this invention, and Fig. 4 shows a conventional one. 2 is an operation timing chart of the majority synchronous control circuit. In the figure, 1 is external circuit a, 2 is external circuit b,
3 is an external circuit c, 4 is a majority circuit, 9 is a counting circuit, 11 is a synchronization control signal generation circuit, 1a is a synchronization signal a output from external circuit 1, and 2a is external circuit 2
3a is the synchronization signal b output from the external circuit 3, 5 is the synchronization signal output from the majority circuit 4, 8 is the majority error signal output from the majority circuit 4, and 10 is the counting circuit. The output signal 9 is a synchronization control signal output from the synchronization control signal generation circuit 11. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
路よりそれぞれ出力される同期信号が入力される
多数決回路、上記多数決回路より出力される多数
決エラー検出信号をクロツク信号とする計数回路
、上記計数回路の出力信号を制御信号とし、上記
外部回路に対し同期制御信号を出力する同期信号
発生回路を備えたことを特徴とする多数決同期制
御回路。 A majority circuit that receives synchronization signals output from three or more external circuits for the purpose of parallel synchronous operation, a counting circuit that uses a majority error detection signal output from the majority circuit as a clock signal, and A majority-voting synchronization control circuit comprising a synchronization signal generation circuit that uses an output signal as a control signal and outputs a synchronization control signal to the external circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP781887U JPS63118647U (en) | 1987-01-22 | 1987-01-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP781887U JPS63118647U (en) | 1987-01-22 | 1987-01-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63118647U true JPS63118647U (en) | 1988-08-01 |
Family
ID=30791627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP781887U Pending JPS63118647U (en) | 1987-01-22 | 1987-01-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63118647U (en) |
-
1987
- 1987-01-22 JP JP781887U patent/JPS63118647U/ja active Pending
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