JPS63149643U - - Google Patents
Info
- Publication number
- JPS63149643U JPS63149643U JP4105087U JP4105087U JPS63149643U JP S63149643 U JPS63149643 U JP S63149643U JP 4105087 U JP4105087 U JP 4105087U JP 4105087 U JP4105087 U JP 4105087U JP S63149643 U JPS63149643 U JP S63149643U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- signal
- converts
- frequency
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の一実施例を示すＤ／Ｆコン
バータの構成図、第２図は実施例のＤ／Ｆコンバ
ータ内で使用する同期クロツクのタイミングを示
す図、第３図は従来のＤ／Ｆコンバータの構成図
、第４図はＤ／Ａコンバータの原理を示す図、第
５図はＶ／Ｆコンバータの原理を示す図である。
図中、１は計算機、２はＤ／Ｆコンバータ、３
はデイジタルデータ、４はＤ／Ａコンバータ、５
はアナログデータ、６はＶ／Ｆコンバータ、７は
周波数データ、８はスイツチ、９は抵抗器、１０
は基準電源、１１は増幅器、１２は積分器、１３
は比較器、１４は放電スイツチ、１５は出力バツ
フア、１６は積分器出力波形、１７は周波数デー
タ波形、１８は分周回路、１９は同期回路、２０
は論理和回路、２１は基準クロツク、２２は同期
クロツクである。なお図中、同一あるいは相当部
分には同一符号を付して示してある。
Fig. 1 is a block diagram of a D/F converter showing an embodiment of this invention, Fig. 2 is a diagram showing the timing of a synchronous clock used in the D/F converter of the embodiment, and Fig. 3 is a diagram showing a conventional D/F converter. FIG. 4 is a diagram showing the principle of a D/A converter, and FIG. 5 is a diagram showing the principle of a V/F converter. In the figure, 1 is a calculator, 2 is a D/F converter, and 3
is digital data, 4 is D/A converter, 5
is analog data, 6 is V/F converter, 7 is frequency data, 8 is switch, 9 is resistor, 10
is a reference power supply, 11 is an amplifier, 12 is an integrator, 13
is a comparator, 14 is a discharge switch, 15 is an output buffer, 16 is an integrator output waveform, 17 is a frequency data waveform, 18 is a frequency dividing circuit, 19 is a synchronization circuit, 20
is an OR circuit, 21 is a reference clock, and 22 is a synchronous clock. In the drawings, the same or corresponding parts are designated by the same reference numerals.
Claims (1)
、アナログ信号に変換するＤ／Ａコンバータと、
上記アナログ信号を周波数信号に変換するＶ／Ｆ
コンバータと、上記周波数信号を位相の異なるク
ロツク信号で同期化する同期回路と、上記同期回
路から出力される複数個の信号を結合させる論理
和回路とを具備したことを特徴とした、デイジタ
ル信号を周波数信号に変換するＤ／Ｆコンバータ
。 A D/A converter that receives parallel digital data from a computer and converts it into an analog signal;
V/F that converts the above analog signal into a frequency signal
A digital signal comprising a converter, a synchronization circuit that synchronizes the frequency signal with a clock signal having a different phase, and an OR circuit that combines a plurality of signals output from the synchronization circuit. D/F converter that converts into frequency signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4105087U JPS63149643U (en) | 1987-03-20 | 1987-03-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4105087U JPS63149643U (en) | 1987-03-20 | 1987-03-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63149643U true JPS63149643U (en) | 1988-10-03 |
Family
ID=30855690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4105087U Pending JPS63149643U (en) | 1987-03-20 | 1987-03-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63149643U (en) |
-
1987
- 1987-03-20 JP JP4105087U patent/JPS63149643U/ja active Pending
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