JPS63105878U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a circuit configuration diagram of a digital peak meter circuit according to an embodiment of this invention, Figures 2 and 3 are circuit diagrams showing conventional digital peak meter circuits, and Figure 4 is the operation of the conventional and this invention. FIG. 3 is a waveform diagram for explaining the above difference. In the figure, 3 is a down counter, 4 is a comparator, 5 is a timer, and 6 is an AND circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of claim for utility model registration] (1) Absolute digital signal (data)
In a digital peak meter that displays and outputs the peak value of A counter control that compares the level of the next data, updates and loads the next data into the down counter only when the next data is large, and stops the counting operation of the down counter for a predetermined period of time when the next data is small. 1. A digital peak meter circuit comprising: a digital peak meter circuit configured to output the output data of the down counter as a display output signal. (2) Registration of a utility model characterized in that the counter control unit is composed of a comparator that compares the output data of the down counter with the next data, a timer that stops the counting operation of the down counter for a predetermined period of time, and an AND circuit. A digital peak meter circuit according to claim 1.