JPH01137635U - - Google Patents
Info
- Publication number
- JPH01137635U JPH01137635U JP3334288U JP3334288U JPH01137635U JP H01137635 U JPH01137635 U JP H01137635U JP 3334288 U JP3334288 U JP 3334288U JP 3334288 U JP3334288 U JP 3334288U JP H01137635 U JPH01137635 U JP H01137635U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- circuit
- frequency signal
- analog data
- converts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第1図はこの考案の一実施例を示すD/Fコン
バータの構成図、第2図は実施例のD/Fコンバ
ータ内で使用する同期クロツクのタイミングを示
す図、第3図は従来のD/Fコンバータの構成図
、第4図はD/Aコンバータの原理を示す図、第
5図a,bはV/Fコンバータの原理を説明する
ための図である。
図中、1は計算機、2はD/Fコンバータ、3
はデイジタルデータ、4はD/Aコンバータ、5
はアナログデータ、6はV/Fコンバータ、7は
周波数データ、8はスイツチ、9は抵抗器、10
は基準電源、11は増幅器、12は積分器、13
は比較器、14は放電スイツチ、15は出力バツ
フア、16は積分器出力波形、17は周波数デー
タ波形、18は分周回路、19は同期回路、20
は論理和回路、21は基準クロツク、22は同期
クロツクである。なお、図中同一あるいは相当部
分には同一符号を付して示してある。
Fig. 1 is a block diagram of a D/F converter showing an embodiment of this invention, Fig. 2 is a diagram showing the timing of a synchronous clock used in the D/F converter of the embodiment, and Fig. 3 is a diagram showing a conventional D/F converter. FIG. 4 is a diagram showing the principle of a D/A converter, and FIGS. 5a and 5b are diagrams explaining the principle of a V/F converter. In the figure, 1 is a calculator, 2 is a D/F converter, and 3
is digital data, 4 is D/A converter, 5
is analog data, 6 is V/F converter, 7 is frequency data, 8 is switch, 9 is resistor, 10
is a reference power supply, 11 is an amplifier, 12 is an integrator, 13
is a comparator, 14 is a discharge switch, 15 is an output buffer, 16 is an integrator output waveform, 17 is a frequency data waveform, 18 is a frequency dividing circuit, 19 is a synchronization circuit, 20
is an OR circuit, 21 is a reference clock, and 22 is a synchronous clock. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.
Claims (1)
換するD/Aコンバータと、上記アナログデータ
を周波数信号に変換するV/Fコンバータと、上
記周波数信号の一部を位相の異なるクロツク信号
で同期化する同期回路と、上記同期回路から出力
される複数個の信号を統合させる論理和回路とを
具備したことを特徴とするD/Fコンバータ。 A D/A converter that converts parallel digital data into analog data, a V/F converter that converts the analog data into a frequency signal, and a synchronization circuit that synchronizes a part of the frequency signal with a clock signal having a different phase. A D/F converter comprising: an OR circuit that integrates a plurality of signals output from the synchronous circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3334288U JPH01137635U (en) | 1988-03-14 | 1988-03-14 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3334288U JPH01137635U (en) | 1988-03-14 | 1988-03-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01137635U true JPH01137635U (en) | 1989-09-20 |
Family
ID=31260004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3334288U Pending JPH01137635U (en) | 1988-03-14 | 1988-03-14 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01137635U (en) |
-
1988
- 1988-03-14 JP JP3334288U patent/JPH01137635U/ja active Pending
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