JPS6415168U - - Google Patents
Info
- Publication number
- JPS6415168U JPS6415168U JP10998887U JP10998887U JPS6415168U JP S6415168 U JPS6415168 U JP S6415168U JP 10998887 U JP10998887 U JP 10998887U JP 10998887 U JP10998887 U JP 10998887U JP S6415168 U JPS6415168 U JP S6415168U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- pulse signal
- comparator
- circuit
- divides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Manipulation Of Pulses (AREA)
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は第１図のブロツク図の構成例を示す回路
図、第３図は入力波形により生成された各サンプ
リングクロツク波形を示す図である。
１…ヒステリシスを有するコンパレータ、２…
分周器、３―１，３―２…インバータ、４…スイ
ツチト・レジスタ回路、５…増幅回路、１３…分
周器。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of the structure of the block diagram in FIG. 1, and FIG. 3 is a diagram showing each sampling clock waveform generated from an input waveform. 1... Comparator with hysteresis, 2...
Frequency divider, 3-1, 3-2... Inverter, 4... Switch register circuit, 5... Amplifier circuit, 13... Frequency divider.
Claims (1)
圧変換回路において、前記入力信号をパルス信号
に変換するヒステリシスを有するコンパレータと
、このコンパレータからのパルス信号を分周する
分周器と、前記コンパレータからのパルス信号と
前記分周器で分周されたパルス信号をサンプリン
グクロツクとするスイツチト・レジスタ回路と、
このスイツチト・レジスタ回路の出力を増幅する
増幅回路とを備えてなることを特徴とする周波数
―電圧変換回路。 A frequency-voltage conversion circuit that converts the frequency of an input signal into a voltage includes a comparator with hysteresis that converts the input signal into a pulse signal, a frequency divider that divides the frequency of the pulse signal from the comparator, and a frequency divider that divides the frequency of the pulse signal from the comparator. a switch register circuit that uses a pulse signal and a pulse signal frequency-divided by the frequency divider as a sampling clock;
A frequency-voltage conversion circuit comprising: an amplifier circuit that amplifies the output of the switch register circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10998887U JPS6415168U (en) | 1987-07-20 | 1987-07-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10998887U JPS6415168U (en) | 1987-07-20 | 1987-07-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6415168U true JPS6415168U (en) | 1989-01-25 |
Family
ID=31346736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10998887U Pending JPS6415168U (en) | 1987-07-20 | 1987-07-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6415168U (en) |
-
1987
- 1987-07-20 JP JP10998887U patent/JPS6415168U/ja active Pending