JPS588231U - Frequency/voltage conversion circuit - Google Patents

Frequency/voltage conversion circuit

Info

Publication number
JPS588231U
JPS588231U JP10255581U JP10255581U JPS588231U JP S588231 U JPS588231 U JP S588231U JP 10255581 U JP10255581 U JP 10255581U JP 10255581 U JP10255581 U JP 10255581U JP S588231 U JPS588231 U JP S588231U
Authority
JP
Japan
Prior art keywords
circuit
signal
analog
frequency
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10255581U
Other languages
Japanese (ja)
Inventor
彰 小林
博美 古賀
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP10255581U priority Critical patent/JPS588231U/en
Publication of JPS588231U publication Critical patent/JPS588231U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示すブロック図、第2図は第
1図の回路の各部の信号のタイムチャートである。 1・・・波形整形回路、2・・・バイナリ−カウンタ、
3・・・デジタル/アナログ変換回路、4・・・サンプ
ルホールド回路、5・・・タイミング回路、6・・・バ
ッファ回路。    ゛
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart of signals of various parts of the circuit shown in FIG. 1... Waveform shaping circuit, 2... Binary counter,
3... Digital/analog conversion circuit, 4... Sample hold circuit, 5... Timing circuit, 6... Buffer circuit.゛

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 人力信号を矩形波又はパルス信号等に整形する波形整形
回路と、この波形整形された信号をカウントし並列信号
に変換するバイナリ−カウンタと、この並列信号に対応
したアナログ信号を出力するデジタル/アナログ変換回
路と、この変換されたアナログ信号の一部をサンプリン
グホールドしアナログ電圧を出力するサンプリングホー
ルド回路及びバッファ回路と、前記バイナリ−カウンタ
回路及びサンプリングホールド回路に必要なタイミング
パルスを発生させるタイミング回路とを備え、入力周波
数に比例したアナログ電圧を作りだすことを特徴とする
周波数/電圧変換回路。
A waveform shaping circuit that shapes a human signal into a rectangular wave or pulse signal, a binary counter that counts this waveform-shaped signal and converts it into a parallel signal, and a digital/analog that outputs an analog signal corresponding to this parallel signal. A conversion circuit, a sampling and holding circuit and a buffer circuit that sample and hold a part of the converted analog signal and output an analog voltage, and a timing circuit that generates timing pulses necessary for the binary counter circuit and the sampling and holding circuit. A frequency/voltage conversion circuit that is equipped with the following and produces an analog voltage proportional to the input frequency.
JP10255581U 1981-07-10 1981-07-10 Frequency/voltage conversion circuit Pending JPS588231U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10255581U JPS588231U (en) 1981-07-10 1981-07-10 Frequency/voltage conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10255581U JPS588231U (en) 1981-07-10 1981-07-10 Frequency/voltage conversion circuit

Publications (1)

Publication Number Publication Date
JPS588231U true JPS588231U (en) 1983-01-19

Family

ID=29897199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10255581U Pending JPS588231U (en) 1981-07-10 1981-07-10 Frequency/voltage conversion circuit

Country Status (1)

Country Link
JP (1) JPS588231U (en)

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