JPH01156470U

JPH01156470U -

Info

Publication number: JPH01156470U
Application number: JP5244888U
Authority: JP
Priority date: 1988-04-19
Filing date: 1988-04-19
Publication date: 1989-10-27

Description

[Brief explanation of the drawing]

第１図は本考案に係るトランスデユーサの一実
施例のブロツク図、第２図は第１図に用いられる
ＰＬＬ回路のブロツク図、第３図は第１図の動作
を説明するための波形図である。Ａ／Ｄ１，Ａ／Ｄ２……アナログ・デイジタル
変換器、ＯＰ……デイジタル演算部、ＰＬＬ……
フエーズ・ロツクド・ループ。 FIG. 1 is a block diagram of an embodiment of a transducer according to the present invention, FIG. 2 is a block diagram of a PLL circuit used in FIG. 1, and FIG. 3 is a waveform diagram for explaining the operation of FIG. 1. It is a diagram. A/D1, A/D2...Analog-digital converter, OP...Digital calculation unit, PLL...
Phase locked loop.

Claims

[Scope of utility model registration request]

In a transducer, the voltage and/or current of a commercial power line is sampled in an analog-to-digital converter, converted into a digital signal, and then added to a digital arithmetic circuit to perform calculations to obtain various amounts of power. PLL that takes the frequency signal on the line as input
A circuit is provided to set the sampling timing clock of the analog-to-digital converter to its PL.
A power transducer characterized in that it is configured to obtain power from an L circuit.