JPS6448615U - - Google Patents

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Publication number
JPS6448615U
JPS6448615U JP14421487U JP14421487U JPS6448615U JP S6448615 U JPS6448615 U JP S6448615U JP 14421487 U JP14421487 U JP 14421487U JP 14421487 U JP14421487 U JP 14421487U JP S6448615 U JPS6448615 U JP S6448615U
Authority
JP
Japan
Prior art keywords
input
signal
signals
inputs
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14421487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14421487U priority Critical patent/JPS6448615U/ja
Publication of JPS6448615U publication Critical patent/JPS6448615U/ja
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す図、第2図
は従来のR/D変換装置を示す図である。 図において、2はアナログ・デイジタル変換器
、4は余弦乗算器、5は正弦乗算器、6は引き算
器、7は乗算器、8は加算器、9はレジスタ、1
1は符号判定器、12は位相検波器、13は電圧
制御発信器、14は可逆カウンタである。なお、
各図中同一符号は同一又は相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional R/D conversion device. In the figure, 2 is an analog-digital converter, 4 is a cosine multiplier, 5 is a sine multiplier, 6 is a subtracter, 7 is a multiplier, 8 is an adder, 9 is a register, 1
1 is a sign determiner, 12 is a phase detector, 13 is a voltage controlled oscillator, and 14 is a reversible counter. In addition,
The same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力端に2相のレゾルバ信号の一方の正弦波の
信号を入力し、デイジタル信号に変換する第1の
アナログ・デイジタル変換器と、入力端に2相の
レゾルバ信号の一方の余弦波の信号を入力し、デ
イジタル信号に変換する第2のアナログ・デイジ
タル変換器と、2つの信号を入力し第1の入力信
号と第2の入力信号の余弦の値と掛け算する余弦
乗算器と、2つの信号を入力し第1の入力信号と
第2の入力信号の正弦の値と掛け算する正弦乗算
器と、2つの信号を入力し2つの信号を引き算す
る引き算器と、2つの信号を入力し2つの信号を
掛け算する乗算器と、2つの信号を入力し、2つ
の信号をたし算する加算器と、2つの信号を入力
し第1の入力信号により、第2の入力信号を一時
保持するレジスタと、入力信号の符号を判定する
符号判定器により構成されたレゾルバ・デイジタ
ル変換装置において、第1の入力端に前記第1の
アナログ・デイジタル変換器の出力信号を入力し
、第2の入力端に前記レジスタの信号を入力し、
第2の入力端の角度の余弦の値を第1の入力端の
信号に掛け算する余弦乗算器と、第1の入力端に
前記第2のアナログ・デイジタル変換器の出力信
号を入力し、第2の入力端に前記レジスタの信号
を入力し、第2の入力端の角度の正弦の値を第1
の入力端の信号に掛け算する正弦乗算器と、2つ
の入力端の第1の入力端に前記余弦乗算器の出力
信号を入力し、第2の入力端に前記正弦乗算器の
出力信号を入力し、2つの信号を引き算する引き
算器と、入力端に基準信号を入力しその符号を判
定する符号判定器と、2つの入力端の第1の入力
端に前記引き算器の出力信号を入力し、第2の入
力端に前記符号判定器の出力信号を入力し、2つ
の信号を掛け合わせる乗算器と、2つの入力端の
第1の入力端に前記レジスタの出力信号を入力し
、第2の入力端に前記乗算器の出力信号を入力し
、2つの信号をたし算する加算器と、2つの入力
端の第1の入力端にクロツク信号を入力し、第2
の入力端に前記加算器の出力信号を入力し第1の
入力端に与えられた信号で第2の入力端に与えら
れた信号を一時保時するレジスタとを備えたこと
を特徴とするレゾルバ・デイジタル変換装置。
A first analog-to-digital converter inputs a sine wave signal of one of the two-phase resolver signals at the input end and converts it into a digital signal, and a cosine wave signal of one of the two-phase resolver signals is input to the input end. a second analog-to-digital converter that receives the input signal and converts it into a digital signal; a cosine multiplier that receives the two signals and multiplies them by the cosine values of the first input signal and the second input signal; a sine multiplier that inputs and multiplies the sine values of the first and second input signals, a subtracter that inputs two signals and subtracts the two signals, and a subtracter that inputs two signals and subtracts the two signals. A multiplier that multiplies signals, an adder that inputs two signals and adds the two signals, and a register that inputs two signals and temporarily holds a second input signal using the first input signal. and a resolver-digital converter comprising a sign determiner for determining the sign of an input signal, the output signal of the first analog-to-digital converter is input to a first input terminal, and the output signal of the first analog-to-digital converter is input to a second input terminal. input the signal of the register into
a cosine multiplier that multiplies the value of the cosine of the angle at the second input end by the signal at the first input end; Input the signal of the register into the second input terminal, and set the value of the sine of the angle at the second input terminal to the first input terminal.
a sine multiplier that multiplies the signal at the input end of the sine multiplier, the output signal of the cosine multiplier is input to the first input end of the two input ends, and the output signal of the sine multiplier is input to the second input end. a subtracter that subtracts two signals; a sign determiner that inputs a reference signal to an input terminal and determines its sign; and an output signal of the subtracter that inputs the output signal of the subtracter to a first input terminal of the two input terminals. , a multiplier that inputs the output signal of the sign determiner to a second input terminal and multiplies the two signals; and a multiplier that inputs the output signal of the register to a first input terminal of the two input terminals, and a second an adder that inputs the output signal of the multiplier to the input terminal of the multiplier and adds the two signals; a clock signal is input to the first input terminal of the two input terminals;
a register that inputs the output signal of the adder to the input terminal of the register and temporarily stores the signal given to the second input terminal with the signal given to the first input terminal.・Digital conversion device.
JP14421487U 1987-09-21 1987-09-21 Pending JPS6448615U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14421487U JPS6448615U (en) 1987-09-21 1987-09-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14421487U JPS6448615U (en) 1987-09-21 1987-09-21

Publications (1)

Publication Number Publication Date
JPS6448615U true JPS6448615U (en) 1989-03-27

Family

ID=31411721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14421487U Pending JPS6448615U (en) 1987-09-21 1987-09-21

Country Status (1)

Country Link
JP (1) JPS6448615U (en)

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