JPH0312115U - - Google Patents

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Publication number
JPH0312115U
JPH0312115U JP7275089U JP7275089U JPH0312115U JP H0312115 U JPH0312115 U JP H0312115U JP 7275089 U JP7275089 U JP 7275089U JP 7275089 U JP7275089 U JP 7275089U JP H0312115 U JPH0312115 U JP H0312115U
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JP
Japan
Prior art keywords
signal
input terminal
input
inputs
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7275089U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7275089U priority Critical patent/JPH0312115U/ja
Publication of JPH0312115U publication Critical patent/JPH0312115U/ja
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第4図はこの考案の一実施例を示す図
、第5図は従来のアナログ・デジタル変換装置を
示す図である。 図において、1はスコツト・トランス、2は象
限選択器、3は余弦乗算器、4は正弦乗算器、5
は引き算器、6は位相検波器、7は電圧制御発振
器、8は可逆カウンタ、9はカウンタ、10はフ
リツププロツプ、11は選択器である。 なお、各図中、同一符号は同一または相当部分を
示す。
1 to 4 are diagrams showing an embodiment of this invention, and FIG. 5 is a diagram showing a conventional analog-to-digital converter. In the figure, 1 is a Scott transformer, 2 is a quadrant selector, 3 is a cosine multiplier, 4 is a sine multiplier, and 5 is a sine multiplier.
is a subtracter, 6 is a phase detector, 7 is a voltage controlled oscillator, 8 is a reversible counter, 9 is a counter, 10 is a flip-prop, and 11 is a selector. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】 (1) 2つの入力端の第1の入力端にレゾルバ信
号の正弦波の信号を入力し第2の入力端に可逆カ
ウンタの出力信号を入力し、上記可逆カウンタの
余弦値を第1の入力端の信号に掛け算する余弦乗
算器と、2つの入力端の第1の入力端にレゾルバ
信号の余弦波の信号を入力し第2の入力端に可逆
カウンタの出力信号を入力し、上記可逆カウンタ
の正弦値を第1の入力端の信号に掛け算する正弦
乗算器と、上記余弦乗算器と上記正弦乗算器の出
力信号を入力し2つの信号の差を出力する引き算
器と、2つの入力端の第1の入力端に上記引き算
器の出力信号を入力し第2の入力端に搬送波を入
力し第1の入力端の信号を第2の入力端の信号で
検波、整流する位相検波器と、上記位相検波器の
出力信号を入力し入力信号により発振周波数が変
化する電圧制御発振器と、上記電圧制御発振器の
クロツク信号を入力しクロツク信号によりカウン
トを行なうカウンタと、上記カウンタの出力信号
により上記電圧制御発振器の出力信号を切り替え
出力する選択器と、2つの入力端の第1の入力端
に上記位相検波器の出力信号を入力し第2の入力
端に上記選択器の出力信号を入力し上昇または下
降のカウントをする上記可逆カウンタとを備えた
ことを特徴とするアナログ・デジタル変換装置。 (2) レゾルバ信号の正弦波と余弦波の信号を入
力し象限選択された正弦波と余弦波の信号を出力
する象限選択器と、2つの入力端の第1の入力端
に上記象限選択器の正弦波の信号を入力し第2の
入力端に可逆カウンタの出力信号を入力し、上記
可逆カウンタの余弦値を第1の入力端の信号に掛
け算する余弦乗算器と、2つの入力端の第1の入
力端に上記象限選択器の余弦波の信号を入力し第
2の入力端に可逆カウンタの出力信号を入力し、
上記可逆カウンタの正弦値を第1の入力端の信号
に掛け算する正弦乗算器と、上記余弦乗算器と上
記正弦乗算器の出力信号を入力し2つの信号の差
を出力する引き算器と、2つの入力端の第1の入
力端に上記引き算器の出力信号を入力し第2の入
力端に搬送波を入力し第1の入力端の信号を第2
の入力端の信号で検波、整流する位相検波器と、
上記位相検波器の出力信号を入力し入力信号によ
り発振周波数が変化する電圧制御発振器と、上記
電圧制御発振器のクロツク信号を入力しクロツク
信号によりカウントを行なうカウンタと、上記カ
ウンタの出力信号により上記電圧制御発振器の出
力信号を切り替え出力する選択器と、2つの入力
端の第1の入力端に上記位相検波器の出力信号を
入力し第2の入力端に上記選択器の出力信号を入
力し上昇または下降のカウントをする上記可逆カ
ウンタとを備えたことを特徴とするアナログ・デ
ジタル変換装置。 (3) 3相のシンクロ信号を入力し2相のレゾル
バ信号に変換するスコツト・トランスと、2つの
入力端の第1の入力端に上記スコツト・トランス
の出力レゾルバ信号の正弦波の信号を入力し第2
の入力端に可逆カウンタの出力信号を入力し、上
記可逆カウンタの余弦値を第1の入力端の信号に
掛け算する余弦乗算器と、2つの入力端の第1の
入力端に上記スコツト・トランスの出力レゾルバ
信号の余弦波の信号を入力し第2の入力端に可逆
カウンタの出力信号を入力し、上記可逆カウンタ
の正弦値を第1の入力端の信号に掛け算する正弦
乗算器と、上記余弦乗算器と上記正弦乗算器の出
力信号を入力し2つの信号の差を出力する引き算
器と、2つの入力端の第1の入力端に上記引き算
器の出力信号を入力し第2の入力端に搬送波を入
力し第1の入力端の信号を第2の入力端の信号で
検波、整流する位相検波器と、上記位相検波器の
出力信号を入力し入力信号により発振周波数が変
化する電圧制御発振器と、上記電圧制御発振器の
クロツク信号を入力しクロツク信号によりカウン
トを行なうカウンタと、上記カウンタの出力信号
により上記電圧制御発振器の出力信号を切り替え
出力する選択器と、2つの入力端の第1の入力端
に上記位相検波器の出力信号を入力し第2の入力
端に上記選択器の出力信号を入力し上昇または下
降のカウントをする上記可逆カウンタとを備えた
ことを特徴とするアナログ・デジタル変換装置。 (4) 3相のシンクロ信号を入力し2相のレゾル
バ信号を出力するスコツト・トランスと、上記ス
コツト・トランスの出力するレゾルバ信号の正弦
波と余弦波の信号を入力し象限選択された正弦波
と余弦波の信号を出力する象限選択器と、2つの
入力端の第1の入力端に上記象限選択器の正弦波
の信号を入力し第2の入力端に可逆カウンタの出
力信号を入力し、上記可逆カウンタの余弦値を第
1の入力端の信号に掛け算する余弦乗算器と、2
つの入力端の第1の入力端に上記象限選択器の余
弦波の信号を入力し第2の入力端に可逆カウンタ
の出力信号を入力し、上記可逆カウンタの正弦値
を第1の入力端の信号に掛け算する正弦乗算器と
、上記余弦乗算器と上記正弦乗算器の出力信号を
入力し2つの信号の差を出力する引き算器と、2
つの入力端の第1の入力端に上記引き算器の出力
信号を入力し第2の入力端に搬送波を入力し第1
の入力端の信号を第2の入力端の信号で検波、整
流する位相検波器と、上記位相検波器の出力信号
を入力し入力信号により発振周波数が変化する電
圧制御発振器と、上記電圧制御発振器のクロツク
信号を入力しクロツク信号によりカウントを行な
うカウンタと、上記カウンタの出力信号により上
記電圧制御発振器の出力信号を切り替え出力する
選択器と、2つの入力端の第1の入力端に上記位
相検波器の出力信号を入力し第2の入力端に上記
選択器の出力信号を入力し上昇または下降のカウ
ントをする上記可逆カウンタとを備えたことを特
徴とするアナログ・デジタル変換装置。
[Claims for Utility Model Registration] (1) A sine wave signal of a resolver signal is inputted to the first input terminal of the two input terminals, an output signal of a reversible counter is inputted to the second input terminal, and the reversible counter A cosine multiplier that multiplies the signal at the first input terminal by the cosine value of , and a cosine wave signal of the resolver signal is input to the first input terminal of the two input terminals, and the output of the reversible counter is input to the second input terminal. A sine multiplier that inputs a signal and multiplies the signal at the first input terminal by the sine value of the reversible counter, inputs the output signals of the cosine multiplier and the sine multiplier, and outputs the difference between the two signals. The output signal of the subtracter is inputted to the first input terminal of the two input terminals, the carrier wave is inputted to the second input terminal, and the signal at the first input terminal is converted into the signal at the second input terminal. A phase detector that performs detection and rectification; a voltage-controlled oscillator that receives the output signal of the phase detector and whose oscillation frequency changes depending on the input signal; and a counter that receives the clock signal of the voltage-controlled oscillator and performs counting based on the clock signal. , a selector that switches and outputs the output signal of the voltage controlled oscillator according to the output signal of the counter; An analog-to-digital conversion device comprising: the reversible counter as described above which inputs the output signal of the selector and counts up or down. (2) A quadrant selector that inputs the sine wave and cosine wave signals of the resolver signal and outputs the quadrant-selected sine wave and cosine wave signals, and the quadrant selector at the first input end of the two input ends. a cosine multiplier that inputs a sine wave signal of , inputs the output signal of a reversible counter to a second input terminal, and multiplies the signal of the first input terminal by the cosine value of the reversible counter; Inputting the cosine wave signal of the quadrant selector into the first input terminal and inputting the output signal of the reversible counter into the second input terminal,
a sine multiplier that multiplies the sine value of the reversible counter by the signal at the first input terminal; a subtracter that inputs the output signals of the cosine multiplier and the sine multiplier and outputs the difference between the two signals; The output signal of the subtracter is inputted to the first input terminal of the two input terminals, the carrier wave is inputted to the second input terminal, and the signal of the first input terminal is inputted to the second input terminal.
a phase detector that detects and rectifies the signal at the input end of the
A voltage controlled oscillator that inputs the output signal of the phase detector and whose oscillation frequency changes depending on the input signal, a counter that inputs the clock signal of the voltage controlled oscillator and performs counting according to the clock signal, and A selector switches and outputs the output signal of the controlled oscillator, and the output signal of the phase detector is input to the first input terminal of the two input terminals, and the output signal of the selector is input to the second input terminal. or the above-mentioned reversible counter that counts the decline. (3) A Scott transformer that inputs a 3-phase synchro signal and converts it into a 2-phase resolver signal, and inputs the sine wave signal of the output resolver signal of the Scott transformer to the first input terminal of the two input terminals. 2nd
a cosine multiplier that inputs the output signal of the reversible counter to the input terminal of the reversible counter and multiplies the signal of the first input terminal by the cosine value of the reversible counter; a sine multiplier that inputs a cosine wave signal of the output resolver signal of the above, inputs the output signal of the reversible counter to a second input terminal, and multiplies the signal of the first input terminal by the sine value of the reversible counter; a cosine multiplier and a subtracter that inputs the output signals of the sine multiplier and outputs the difference between the two signals; a subtracter that inputs the output signal of the subtracter to a first input terminal of the two input terminals; A phase detector that inputs a carrier wave at one end and detects and rectifies the signal at the first input end with the signal at the second input end, and a voltage whose oscillation frequency changes depending on the input signal to which the output signal of the phase detector is input. a controlled oscillator; a counter that receives the clock signal of the voltage controlled oscillator and performs counting according to the clock signal; a selector that switches and outputs the output signal of the voltage controlled oscillator based on the output signal of the counter; An analog device characterized in that it is equipped with the reversible counter that inputs the output signal of the phase detector to one input terminal, inputs the output signal of the selector to the second input terminal, and counts up or down.・Digital conversion device. (4) A SCOTT transformer that inputs a 3-phase synchro signal and outputs a 2-phase resolver signal, and a sine wave whose quadrant is selected by inputting the sine wave and cosine wave signals of the resolver signal output from the SCOTT transformer. and a quadrant selector that outputs a cosine wave signal, the sine wave signal of the quadrant selector is input to the first input terminal of the two input terminals, and the output signal of the reversible counter is input to the second input terminal. , a cosine multiplier that multiplies the cosine value of the reversible counter by the signal at the first input terminal;
The cosine wave signal of the quadrant selector is input to the first input terminal of the two input terminals, the output signal of the reversible counter is input to the second input terminal, and the sine value of the reversible counter is input to the first input terminal. a sine multiplier that multiplies the signal; a subtracter that inputs the output signals of the cosine multiplier and the sine multiplier and outputs the difference between the two signals;
The output signal of the subtracter is inputted to the first input terminal of the two input terminals, the carrier wave is inputted to the second input terminal, and the carrier wave is inputted to the second input terminal.
a phase detector that detects and rectifies the signal at the input end of the input terminal using the signal at the second input terminal; a voltage controlled oscillator that receives the output signal of the phase detector and whose oscillation frequency changes depending on the input signal; and the voltage controlled oscillator. a counter that inputs a clock signal and performs counting according to the clock signal; a selector that switches and outputs the output signal of the voltage controlled oscillator based on the output signal of the counter; 1. An analog-to-digital converter comprising: the reversible counter which inputs the output signal of the selector and inputs the output signal of the selector to a second input terminal and counts up or down.
JP7275089U 1989-06-21 1989-06-21 Pending JPH0312115U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7275089U JPH0312115U (en) 1989-06-21 1989-06-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7275089U JPH0312115U (en) 1989-06-21 1989-06-21

Publications (1)

Publication Number Publication Date
JPH0312115U true JPH0312115U (en) 1991-02-07

Family

ID=31610965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7275089U Pending JPH0312115U (en) 1989-06-21 1989-06-21

Country Status (1)

Country Link
JP (1) JPH0312115U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5122878U (en) * 1974-08-09 1976-02-19
JPS5255683U (en) * 1975-10-20 1977-04-21

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5122878U (en) * 1974-08-09 1976-02-19
JPS5255683U (en) * 1975-10-20 1977-04-21

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