JPS6448614U - - Google Patents

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Publication number
JPS6448614U
JPS6448614U JP14421387U JP14421387U JPS6448614U JP S6448614 U JPS6448614 U JP S6448614U JP 14421387 U JP14421387 U JP 14421387U JP 14421387 U JP14421387 U JP 14421387U JP S6448614 U JPS6448614 U JP S6448614U
Authority
JP
Japan
Prior art keywords
input
signal
signals
input terminal
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14421387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14421387U priority Critical patent/JPS6448614U/ja
Publication of JPS6448614U publication Critical patent/JPS6448614U/ja
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す図、第2図
は従来のR/D変換装置を示す図である。 図において、2はアナログ・デイジタル変換器
、3は象限選択回路、4は余弦乗算器、5は正弦
乗算器、6は引き算器、7は乗算器、8は加算器
、9はレジスタ、11は符号判定器、12は位相
検波器、13は電圧制御発信器、14は可逆カウ
ンタである。なお、各図中同一符号は同一又は相
当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional R/D conversion device. In the figure, 2 is an analog-to-digital converter, 3 is a quadrant selection circuit, 4 is a cosine multiplier, 5 is a sine multiplier, 6 is a subtracter, 7 is a multiplier, 8 is an adder, 9 is a register, and 11 is a 12 is a phase detector, 13 is a voltage controlled oscillator, and 14 is a reversible counter. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力端に2相のレゾルバ信号の一方の正弦波の
信号を入力し、デイジタル信号に変換する第1の
アナログ・デイジタル変換器と、入力端に、2相
のレゾルバ信号の一方の余弦波の信号を入力し、
デイジタル信号に変換する第2のアナログ・デイ
ジタル変換器と、2つの入力端を有し、その第1
の入力端に前記第1のアナログ・デイジタル変換
器の出力信号を入力し、第2の入力端に前記第2
のアナログ・デイジタル変換器の出力信号を入力
し、角度の象限により2つの信号を出力する象限
選択回路と、2つの信号を入力し第1の入力信号
と第2の入力信号の余弦の値と掛け算する余弦乗
算器と、2つの信号を入力し第1の入力信号と第
2の入力信号の正弦の値と掛け算する正弦乗算器
と、2つの信号を入力し2つの信号を引き算する
引き算器と、2つの信号を入力し2つの信号を掛
け算する乗算器と、2つの信号を入力し、2つの
信号をたし算する加算器と、2つの信号を入力し
第1の入力信号により、第2の入力信号を一時保
持するレジスタと、入力信号の符号を判定する符
号判定器により構成されたレゾルバ・デイジタル
変換装置において、第1の入力端に前記象限選択
回路の2つの出力信号の一方の正弦波を入力し、
第2の入力端に前記レジスタの信号を入力し、第
2の入力端の角度の余弦の値を第1の入力端の信
号に掛け算する余弦乗算器と、第1の入力端に前
記象限選択回路の2つの出力信号の一方の余弦波
を入力し、第2の入力端に前記レジスタの信号を
入力し、第2の入力端の角度の正弦の値を第1の
入力端の信号に掛け算する正弦乗算器と、2つの
入力端の第1の入力端に前記余弦乗算器の出力信
号を入力し、第2の入力端に前記正弦乗算器の出
力信号を入力し、2つの信号を引き算する引き算
器と、入力端に基準信号を入力しその符号を判定
する符号判定器と、2つの入力端の第1の入力端
に前記引き算器の出力信号を入力し、第2の入力
端に前記符号判定器の出力信号を入力し、2つの
信号を掛け合わせる乗算器と、2つの入力端の第
1の入力端に前記レジスタの出力信号を入力し、
第2の入力端に前記乗算器の出力信号を入力し、
2つの信号をたし算する加算器と、2つの入力端
の第1の入力端にクロツク信号を入力し、第2の
入力端に前記加算器の出力信号を入力し第1の入
力端に与えられた信号で第2の入力端に与えられ
た信号を一時保時するレジスタとを備えたことを
特徴とするレゾルバ・デイジタル変換装置。
a first analog-to-digital converter which inputs one sine wave signal of the two-phase resolver signal at the input end and converts it into a digital signal; and a cosine wave signal of one of the two-phase resolver signals at the input end. Enter
a second analog-to-digital converter for converting into a digital signal and having two inputs;
The output signal of the first analog-to-digital converter is input to the input terminal of the converter, and the output signal of the first analog-to-digital converter is input to the input terminal of
A quadrant selection circuit inputs the output signal of an analog-to-digital converter and outputs two signals according to the angular quadrant; A cosine multiplier that multiplies, a sine multiplier that receives two signals and multiplies them by the sine values of the first and second input signals, and a subtractor that receives two signals and subtracts the two signals. , a multiplier that inputs two signals and multiplies the two signals, an adder that inputs two signals and adds the two signals, and a first input signal that inputs the two signals, In a resolver/digital conversion device configured with a register that temporarily holds a second input signal and a sign determiner that determines the sign of the input signal, one of the two output signals of the quadrant selection circuit is connected to the first input terminal. Input the sine wave of
a cosine multiplier that inputs the signal of the register at a second input terminal and multiplies the signal at the first input terminal by the value of the cosine of the angle at the second input terminal; and the quadrant selection terminal at the first input terminal. Input the cosine wave of one of the two output signals of the circuit, input the signal of the register to the second input terminal, and multiply the signal of the first input terminal by the value of the sine of the angle at the second input terminal. a sine multiplier that inputs the output signal of the cosine multiplier to the first input terminal of the two input terminals, inputs the output signal of the sine multiplier to the second input terminal, and subtracts the two signals. a subtracter that inputs a reference signal to an input terminal and determines its sign; a multiplier that inputs the output signal of the sign determiner and multiplies the two signals; and inputs the output signal of the register to a first input terminal of the two input terminals;
inputting the output signal of the multiplier to a second input terminal;
an adder that adds two signals; a clock signal is input to a first input terminal of the two input terminals; an output signal of the adder is input to a second input terminal; 1. A resolver digital conversion device comprising: a register for temporarily holding a signal applied to a second input terminal with a given signal.
JP14421387U 1987-09-21 1987-09-21 Pending JPS6448614U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14421387U JPS6448614U (en) 1987-09-21 1987-09-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14421387U JPS6448614U (en) 1987-09-21 1987-09-21

Publications (1)

Publication Number Publication Date
JPS6448614U true JPS6448614U (en) 1989-03-27

Family

ID=31411719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14421387U Pending JPS6448614U (en) 1987-09-21 1987-09-21

Country Status (1)

Country Link
JP (1) JPS6448614U (en)

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