JPH0189317U - - Google Patents

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Publication number
JPH0189317U
JPH0189317U JP18472987U JP18472987U JPH0189317U JP H0189317 U JPH0189317 U JP H0189317U JP 18472987 U JP18472987 U JP 18472987U JP 18472987 U JP18472987 U JP 18472987U JP H0189317 U JPH0189317 U JP H0189317U
Authority
JP
Japan
Prior art keywords
signal
input terminal
input
signals
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18472987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18472987U priority Critical patent/JPH0189317U/ja
Publication of JPH0189317U publication Critical patent/JPH0189317U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)
  • Transmission And Conversion Of Sensor Element Output (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す図、第2図
は従来のR/D変換装置を示す図である。 図において、2はアナログ・デイジタル変換器
、3は象限選択回路、4は余弦乗算器、5は正弦
乗算器、6は引き算器、8は選択器、8は加算器
、9はレジスタ、11は符号判定器、12は位相
検波器、13は電圧制御発信器、14は可逆カウ
ンタ、15は符号反転器である。なお、各図中同
一符号は同一又は相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional R/D conversion device. In the figure, 2 is an analog-to-digital converter, 3 is a quadrant selection circuit, 4 is a cosine multiplier, 5 is a sine multiplier, 6 is a subtracter, 8 is a selector, 8 is an adder, 9 is a register, and 11 is a 12 is a phase detector, 13 is a voltage controlled oscillator, 14 is a reversible counter, and 15 is a sign inverter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力端に2相のレゾルバ信号の一方の正弦波の
信号を入力し、デイジタル信号に変換する第1の
アナログ・デイジタル変換器と、入力端に、2相
のレゾルバ信号の一方の余弦波の信号を入力し、
デイジタル信号に変換する第2のアナログ・デイ
ジタル変換器と、2つの入力端を有し、その第1
の入力端に前記第1のアナログ・デイジタル変換
器の出力信号を入力し、第2の入力端に前記第2
のアナログ・デイジタル変換器の出力信号を入力
し、角度の象限により2つの信号を出力する象限
選択回路と、2つの信号を入力し第1の入力信号
と第2の入力信号の余弦の値と掛け算する余弦乗
算器と、2つの信号を入力し第1の入力信号と第
2の入力信号の正弦の値と掛け算する正弦乗算器
と、2つの信号を入力し2つの信号を引き算する
引き算器と、1つの信号を入力しその符号を反転
する符号反転器と、2つの信号を入力しその一方
を選択出力する選択器と、2つの信号を入力し、
2つの信号をたし算する加算器と、2つの信号を
入力し、第1の入力信号により、第2の入力信号
を一時保持するレジスタと、入力信号の符号を判
定する符号判定器により構成されたレゾルバ・デ
イジタル変換装置において、第1の入力端に前記
象限選択回路の2つの出力信号の一方の正弦波を
入力し、第2の入力端に前記レジスタの信号を入
力し、第2の入力端の角度の余弦の値を第1の入
力端の信号に掛け算する余弦乗算器と、第1の入
力端に前記象限選択回路の2つの出力信号の一方
の余弦波を入力し、第2の入力端を前記レジスタ
の信号を入力し、第2の入力端の角度の正弦の値
を第1の入力端の信号に掛け算する正弦乗算器と
、2つの入力端の第1の入力端に前記余弦乗算器
の出力信号を入力し、第2の入力端に前記正弦乗
算器の出力信号を入力し、2つの信号を引き算す
る引き算器と、入力端に前記引き算器の出力信号
を入力し符号を反転する符号反転器と、入力端に
基準信号を入力しその符号を判定する符号判定器
と、3つの入力端の第1の入力端に前記引き算器
の出力信号を入力し、第2の入力端に前記符号反
転器の出力信号を入力し、第3の入力端に前記符
号判定器の出力信号を入力し、第3の入力端に与
えられた信号により第1の入力端に与えられた信
号又は第2の入力端に与えられた信号を選らび出
力する選択器と、2つの入力端の第1の入力端に
前記レジスタの出力信号を入力し、第2の入力端
に前記選択器の出力信号を入力し、2つの信号を
たし算する加算器と、2つの入力端の第1の入力
端にクロツク信号を入力し、第2の入力端に前記
加算器の出力信号を入力し第1の入力端に与えら
れた信号で第2の入力端に与えられた信号を一時
保持するレジスタとを備えたことを特徴とするレ
ゾルバ・デイジタル変換装置。
a first analog-to-digital converter which inputs one sine wave signal of the two-phase resolver signal at the input end and converts it into a digital signal; and a cosine wave signal of one of the two-phase resolver signals at the input end. Enter
a second analog-to-digital converter for converting into a digital signal and having two inputs;
The output signal of the first analog-to-digital converter is input to the input terminal of the converter, and the output signal of the first analog-to-digital converter is input to the input terminal of
A quadrant selection circuit inputs the output signal of an analog-to-digital converter and outputs two signals according to the angular quadrant; A cosine multiplier that multiplies, a sine multiplier that receives two signals and multiplies them by the sine values of the first and second input signals, and a subtractor that receives two signals and subtracts the two signals. , a sign inverter that inputs one signal and inverts its sign, and a selector that inputs two signals and selects and outputs one of them;
Consists of an adder that adds two signals, a register that inputs the two signals and temporarily holds the second input signal based on the first input signal, and a sign determiner that determines the sign of the input signal. In the resolver/digital conversion device, one of the two output signals of the quadrant selection circuit is inputted to the first input terminal, the signal of the register is inputted to the second input terminal, and the sine wave of one of the two output signals of the quadrant selection circuit is inputted to the second input terminal. a cosine multiplier that multiplies the value of the cosine of the angle at the input end by the signal at the first input end; a sine multiplier that inputs the signal of the register to the input terminal of the register and multiplies the signal of the first input terminal by the value of the sine of the angle of the second input terminal; A subtracter that inputs the output signal of the cosine multiplier, inputs the output signal of the sine multiplier to a second input terminal, and subtracts the two signals, and inputs the output signal of the subtracter to the input terminal. a sign inverter for inverting the sign; a sign determiner for inputting a reference signal to an input terminal and determining the sign thereof; The output signal of the sign inverter is input to the input terminal of the sign inverter, the output signal of the sign determiner is input to the third input terminal, and the signal applied to the third input terminal is applied to the first input terminal. a selector that selects and outputs the signal given to the input terminal or the signal given to the second input terminal; the output signal of the register is input to the first input terminal of the two input terminals; an adder that inputs the output signal of the selector and adds the two signals; a clock signal is input to the first input terminal of the two input terminals; and the output signal of the adder is input to the second input terminal; What is claimed is: 1. A resolver digital conversion device comprising: a register for inputting a signal applied to a first input terminal and temporarily holding a signal applied to a second input terminal;
JP18472987U 1987-12-03 1987-12-03 Pending JPH0189317U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18472987U JPH0189317U (en) 1987-12-03 1987-12-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18472987U JPH0189317U (en) 1987-12-03 1987-12-03

Publications (1)

Publication Number Publication Date
JPH0189317U true JPH0189317U (en) 1989-06-13

Family

ID=31476070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18472987U Pending JPH0189317U (en) 1987-12-03 1987-12-03

Country Status (1)

Country Link
JP (1) JPH0189317U (en)

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