JPH01105810U

JPH01105810U -

Info

Publication number: JPH01105810U
Application number: JP181088U
Authority: JP
Priority date: 1988-01-11
Filing date: 1988-01-11
Publication date: 1989-07-17

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示す図、第２図
は従来のＳ／Ｄ変換装置を示す図、第３図は基準
信号が０の場合シンクロ信号とデイジタル値が０
〜９０度の範囲の記憶器のデータを示す図、第４
図は基準信号が１の場合シンクロ信号とデイジタ
ル値が０〜９０度の範囲の記憶器のデータを示す
図である。図において、１はスコツト・トランス、２はア
ナログ・デイジタル変換器、４は記憶器、５はト
ランス、６は符号判定器、７は加算器、８はレジ
スタ、９は余弦乗算器、１０は正弦乗算器、１１
は引き算器、１２は位相検波器、１３は電圧制御
発振器、１４は可逆カウンタである。なお、各図
中同一符号は同一又は相当部分を示す。 Fig. 1 shows an embodiment of this invention, Fig. 2 shows a conventional S/D converter, and Fig. 3 shows that when the reference signal is 0, the synchro signal and digital value are 0.
Figure 4 showing data of the memory device in the range of ~90 degrees
The figure is a diagram showing the synchronization signal and the data of the memory in the range of 0 to 90 degrees when the reference signal is 1. In the figure, 1 is a Scott transformer, 2 is an analog-to-digital converter, 4 is a memory, 5 is a transformer, 6 is a sign determiner, 7 is an adder, 8 is a register, 9 is a cosine multiplier, and 10 is a sine multiplier, 11
is a subtracter, 12 is a phase detector, 13 is a voltage controlled oscillator, and 14 is a reversible counter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A Scotto transformer or a conversion circuit that inputs a 3-phase synchro signal and converts it into a 2-phase resolver signal, and 2 outputs of the Scotto transformer at the input end.
A first analog-to-digital converter inputs a sine wave signal of one of the two-phase resolver signals and converts it into a digital signal; A second analog-to-digital converter inputs a signal and converts it into a digital signal; a sign determiner inputs a reference signal to its input terminal and determines its sign; and a sign determiner inputs an address signal and converts the data specified by the address. A memory device to output and input two signals to 2
In a synchro-digital conversion device, which is configured with an adder that outputs the sum of two signals, and a register that inputs two signals and temporarily holds the second input signal according to the first input signal, the four input terminals are inputting a sine wave of the output signal of the first analog-to-digital converter to a first input terminal, inputting a cosine wave of the output signal of the second analog-to-digital converter to a second input terminal; A storage device that inputs the signal of the register to a third input terminal, inputs the signal of the sign determiner to a fourth input terminal, and outputs the stored data according to the four input signals; an adder that inputs the output signal of the storage device to a first input terminal, inputs the output signal of the register to a second input terminal, and adds the two signals; Input the clock signal to the input terminal, and
The synchronizer is characterized in that it is provided with a register that inputs the output signal of the adder to the input terminal of the register and temporarily holds the signal given to the second input terminal with the signal given to the first input terminal. Digital conversion device.