JPH0255119U

JPH0255119U -

Info

Publication number: JPH0255119U
Application number: JP13356688U
Authority: JP
Priority date: 1988-10-13
Filing date: 1988-10-13
Publication date: 1990-04-20

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を示す図、第２図
は従来のＲ／Ｄ変換装置を示す図である。図において、２はアナログ・デイジタル変換器
、３は象限選択回路、４は余弦乗算器、５は正弦
乗算器、６は引き算器、７は撰択器、８は加算器
、９はレジスタ、１１は排他的論理和ゲート、１
２は位相検波器、１３は電圧制御発振器、１４は
可逆カウンタ、１５は符号反転器である。なお、
各図中同一符号は同一又は相当部分を示す。 FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional R/D conversion device. In the figure, 2 is an analog-digital converter, 3 is a quadrant selection circuit, 4 is a cosine multiplier, 5 is a sine multiplier, 6 is a subtracter, 7 is a selector, 8 is an adder, 9 is a register, 11 is an exclusive OR gate, 1
2 is a phase detector, 13 is a voltage controlled oscillator, 14 is a reversible counter, and 15 is a sign inverter. In addition,
The same reference numerals in each figure indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

a first analog-to-digital converter which inputs one sine wave signal of the two-phase resolver signal at the input end and converts it into a digital signal; and a cosine wave signal of one of the two-phase resolver signals at the input end. Enter
a second analog-to-digital converter for converting the digital signal into a digital signal;
The output signal of the first analog-to-digital converter is input to the input terminal of the converter, and the output signal of the first analog-to-digital converter is input to the input terminal of
A quadrant selection circuit inputs the output signal of an analog-to-digital converter and outputs two signals according to the angular quadrant; A cosine multiplier that multiplies, a sine multiplier that receives two signals and multiplies them by the sine values of the first and second input signals, and a subtractor that receives two signals and subtracts the two signals. , a sign inverter that inputs one signal and inverts its sign, and a selector that inputs two signals and selects and outputs one of them;
An adder that adds two signals, a register that inputs two signals and temporarily holds a second input signal according to the first input signal, and an exclusive register that outputs the exclusive OR of the two signals. In a resolver digital switching device composed of logical OR gates,
The sine wave of one of the two output signals of the quadrant selection circuit is input to the first input terminal, the signal of the register is input to the second input terminal, and the value of the cosine of the angle at the second input terminal is input. a cosine multiplier for multiplying the signal at the first input terminal; and a cosine multiplier for multiplying the signal at the first input terminal;
Sine multiplication that inputs one cosine wave of two output signals, inputs the signal of the register to the second input terminal, and multiplies the signal of the first input terminal by the value of the sine of the angle at the second input terminal. an output signal of the cosine multiplier is input to a first input terminal of the two input terminals, an output signal of the sine multiplier is input to a second input terminal of the two input terminals;
a subtracter that subtracts two signals; a sign inverter that inputs the output signal of the subtracter to an input terminal and inverts the sign; Input the reference signal to
An exclusive OR gate outputs the exclusive OR of two signals, the output signal of the subtracter is input to the first input terminal of the three input terminals, and the output signal of the sign inverter is input to the second input terminal. inputting an output signal, inputting an output signal of the exclusive OR gate to a third input terminal,
a selector that selects and outputs the signal given to the first input terminal or the signal given to the second input terminal according to the signal given to the third input terminal; and a first input of the two input terminals; an adder that inputs the output signal of the register at one end, inputs the output signal of the selector at a second input end, and adds the two signals; A clock signal is input to the second input terminal, and the output signal of the adder is input to the first input terminal.
1. A resolver digital conversion device comprising: a register for temporarily holding a signal applied to an input terminal of the first input terminal; and a register temporarily holding a signal applied to a second input terminal.