JPH0189319U - - Google Patents

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Publication number
JPH0189319U
JPH0189319U JP18519187U JP18519187U JPH0189319U JP H0189319 U JPH0189319 U JP H0189319U JP 18519187 U JP18519187 U JP 18519187U JP 18519187 U JP18519187 U JP 18519187U JP H0189319 U JPH0189319 U JP H0189319U
Authority
JP
Japan
Prior art keywords
signal
input terminal
inputs
input
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18519187U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18519187U priority Critical patent/JPH0189319U/ja
Publication of JPH0189319U publication Critical patent/JPH0189319U/ja
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示す図、第2図
は従来のS/D変換装置を示す図である。 図において1はスコツト・トランス、2はアナ
ログ・デイジタル変換器、3は象限選択回路、4
は余弦乗算器、5は正弦乗算器、6は引き算器、
7は選択器、8は加算器、9はレジスタ、10は
トランス、11は符号判定器、12は位相検波器
、13は電圧制御発信器、14は可逆カウンタ、
15は符号反転器である。なお、各図中同一符号
は同一又は相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional S/D conversion device. In the figure, 1 is a Scott transformer, 2 is an analog-to-digital converter, 3 is a quadrant selection circuit, and 4 is a quadrant selection circuit.
is a cosine multiplier, 5 is a sine multiplier, 6 is a subtracter,
7 is a selector, 8 is an adder, 9 is a register, 10 is a transformer, 11 is a sign determiner, 12 is a phase detector, 13 is a voltage controlled oscillator, 14 is a reversible counter,
15 is a sign inverter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 3相のシンクロ信号を入力し、2相のレゾルバ
信号に変換するスコツト・トランス又は変換回路
と、入力端に前記スコツト・トランスの出力の2
相のレゾルバ信号の一方の正弦波の信号を入力し
、デイジタル信号に変換する第1のアナログ・デ
イジタル変換器と、入力端に前記スコツト・トラ
ンス出力の2相のレゾルバ信号の一方の余弦波の
信号を入力し、デイジタル信号に変換する第2の
アナログ・デイジタル変換器と、2つの入力端を
有し、その第1の入力端に前記第1のアナログ・
デイジタル変換器の出力信号を入力し、第2の入
力端に前記第2のアナログ・デイジタル変換器の
出力信号を入力し、角度の象限により2つの信号
を出力する象限選択回路と、2つの信号を入力し
第1の入力信号と第2の入力信号の余弦の値と掛
け算する余弦乗算器と、2つの信号を入力し、第
1の人力信号と第2の入力信号の正弦の値と掛け
算する正弦乗算器と、2つの信号を入力し2つの
信号を引き算する引き算器と、1つの信号を入力
しその符号を反転する符号反転器と2つの信号を
入力しその一方を選択出力する選択器と、2つの
信号を入力し2つの信号をたし算する加算器と、
2つの信号を入力し第1の入力信号により、第2
の入力信号を一時保持するレジスタと、入力信号
の符号を判定する符号判定器により構成されたシ
ンクロ・デイジタル変換装置において、第1の入
力端に前記象限選択回路の2つの出力信号の一方
の正弦波を入力し、第2の入力端に前記レジスタ
の信号を入力し、第2の入力端の角度の余弦の値
を第1の入力端の信号に掛け算する余弦乗算器と
、第1の入力端に前記象限選択回路の2つの出力
信号の一方の余弦波を入力し、第2の入力端に前
記レジスタの信号を入力し、第2の入力端の角度
の正弦の値を第1の入力端の信号に掛け算する正
弦乗算器と、2つの入力端の第1の入力端に前記
余弦乗算器の出力信号を入力し、第2の入力端に
前記正弦乗算器の出力信号を入力し、2つの信号
を引き算する引き算器と、入力端に前記引き算器
の出力を入力し符号を反転する符号反転器と、入
力端に基準信号を入力しその符号を判定する符号
判定器と、3つの入力端の第1の入力端に前記引
き算器の出力信号を入力し、第2の入力端に前記
符号反転器の出力信号を入力し、第3の入力端に
前記符号判定器の出力信号を入力し、第3の入力
端に与えられた信号により第1の入力端に与えら
れた信号又第2の入力端に与えられた信号を選ら
び出力する選択器と、2つの入力端の第1の入力
端に前記レジスタの出力信号を入力し、第2の入
力端に前記選択器の出力信号を入力し、2つの信
号をたし算する加算器と、2つの入力端の第1の
入力端にクロツク信号を入力し、第2の入力端に
前記加算器の出力信号を入力し第1の入力端に与
えられた信号で第2の入力端に与えられた信号を
一時保持するレジスタとを備えたことを特徴とす
るシンクロ・デイジタル変換装置。
A Scotto transformer or a conversion circuit that inputs a 3-phase synchro signal and converts it into a 2-phase resolver signal, and 2 outputs of the Scotto transformer at the input end.
A first analog-to-digital converter inputs a sine wave signal of one of the two-phase resolver signals and converts it into a digital signal; a second analog-to-digital converter for inputting a signal and converting it into a digital signal; and a second analog-to-digital converter for inputting a signal and converting it into a digital signal;
a quadrant selection circuit that inputs an output signal of a digital converter, inputs an output signal of the second analog-to-digital converter to a second input terminal, and outputs two signals according to an angular quadrant; a cosine multiplier that inputs and multiplies by the cosine value of the first input signal and the second input signal; A sine multiplier that inputs two signals and subtracts the two signals, a sign inverter that inputs one signal and inverts its sign, and a selection that inputs two signals and selects and outputs one of them. an adder that inputs two signals and adds the two signals;
When two signals are input, the first input signal causes the second
In a synchro-digital converter, the synchro-digital converter is configured with a register that temporarily holds an input signal, and a sign determiner that determines the sign of the input signal. a cosine multiplier that inputs a wave, inputs the signal of the register to a second input terminal, and multiplies the signal of the first input terminal by the value of the cosine of the angle at the second input terminal; The cosine wave of one of the two output signals of the quadrant selection circuit is input to one end, the signal of the register is input to the second input end, and the value of the sine of the angle at the second input end is input to the first input end. a sine multiplier that multiplies the signal at the end; a first input terminal of the two input terminals receives the output signal of the cosine multiplier, and a second input terminal receives the output signal of the sine multiplier; A subtracter that subtracts two signals, a sign inverter that inputs the output of the subtracter to its input terminal and inverts its sign, and a sign determiner that inputs a reference signal to its input terminal and determines its sign. The output signal of the subtracter is inputted to a first input terminal of the input terminals, the output signal of the sign inverter is inputted to a second input terminal, and the output signal of the sign determiner is inputted to a third input terminal. a selector that selects and outputs the signal given to the first input terminal or the signal given to the second input terminal according to the signal given to the third input terminal; an adder that inputs the output signal of the register to one input terminal, inputs the output signal of the selector to a second input terminal, and adds the two signals; A register that inputs a clock signal to an input terminal, inputs the output signal of the adder to a second input terminal, and temporarily holds the signal given to the second input terminal with the signal given to the first input terminal. A synchro-digital conversion device characterized by comprising:
JP18519187U 1987-12-04 1987-12-04 Pending JPH0189319U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18519187U JPH0189319U (en) 1987-12-04 1987-12-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18519187U JPH0189319U (en) 1987-12-04 1987-12-04

Publications (1)

Publication Number Publication Date
JPH0189319U true JPH0189319U (en) 1989-06-13

Family

ID=31476517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18519187U Pending JPH0189319U (en) 1987-12-04 1987-12-04

Country Status (1)

Country Link
JP (1) JPH0189319U (en)

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